參數(shù)資料
型號(hào)： PCA9557BS,118
廠商： NXP Semiconductors
文件頁(yè)數(shù)： 30/30頁(yè)
文件大?。?/td> 0K
描述： IC I/O EXPANDER I2C 8B 16HVQFN
產(chǎn)品培訓(xùn)模塊： I²C Bus Fundamentals
特色產(chǎn)品： NXP - I2C Interface
標(biāo)準(zhǔn)包裝： 1
接口： I²C，SM 總線
輸入/輸出數(shù)： 8
中斷輸出： 無(wú)
頻率 - 時(shí)鐘： 400kHz
電源電壓： 2.3 V ~ 5.5 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 16-VQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 16-HVQFN
包裝： 標(biāo)準(zhǔn)包裝
包括： POR
產(chǎn)品目錄頁(yè)面： 826 (CN2011-ZH PDF)
其它名稱： 568-3398-6
PCA9557
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 7 — 10 December 2013
9 of 30
NXP Semiconductors
PCA9557
8-bit I2C-bus and SMBus I/O port with reset
7.4 Power-on reset
When power is applied to VDD, an internal Power-On Reset (POR) holds the PCA9557 in
a reset condition until VDD has reached VPOR. At that point, the reset condition is released
and the PCA9557 registers and I2C-bus/SMBus state machine will initialize to their default
states. Thereafter, VDD must be lowered below 0.2 V to reset the device.
7.5 RESET input
A reset can be accomplished by holding the RESET pin LOW for a minimum of tw(rst). The
PCA9557 registers and SMBus/I2C-bus state machine will be held in their default state
until the RESET input is once again HIGH. This input requires a pull-up resistor to VDD if
no active connection is used.
8.
Characteristics of the I2C-bus
The I2C-bus is for 2-way, 2-line communication between different ICs or modules. The two
lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be
connected to a positive supply via a pull-up resistor when connected to the output stages
of a device. Data transfer may be initiated only when the bus is not busy.
8.1 Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
will be interpreted as control signals (see Figure 10).
8.1.1 START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW
transition of the data line while the clock is HIGH is defined as the START condition (S). A
LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP
condition (P) (see Figure 11).
Fig 10. Bit transfer
mba607
data line
stable;
data valid
change
of data
allowed
SDA
SCL
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