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參數(shù)資料
型號(hào)： PCA9555HF,118
廠商： NXP Semiconductors
文件頁(yè)數(shù)： 33/34頁(yè)
文件大?。?/td> 0K
描述： IC I/O EXPANDER I2C 16B 24HWQFN
標(biāo)準(zhǔn)包裝： 6,000
接口： I²C，SM 總線
輸入/輸出數(shù)： 16
中斷輸出： 是
頻率 - 時(shí)鐘： 400kHz
電源電壓： 2.3 V ~ 5.5 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 24-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 24-HWQFN（4x4）
包裝： 帶卷 (TR)
包括： POR
其它名稱： 935284458118
PCA9555HF-T
PCA9555HF-T-ND
PCA9555_8
NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 08 — 22 October 2009
8 of 34
NXP Semiconductors
PCA9555
16-bit I2C-bus and SMBus I/O port with interrupt
6.2.5 Registers 6 and 7: Conguration registers
This register congures the directions of the I/O pins. If a bit in this register is set (written
with ‘1’), the corresponding port pin is enabled as an input with high-impedance output
driver. If a bit in this register is cleared (written with ‘0’), the corresponding port pin is
enabled as an output. Note that there is a high value resistor tied to VDD at each pin. At
reset, the device's ports are inputs with a pull-up to VDD.
6.3 Power-on reset
When power is applied to VDD, an internal power-on reset holds the PCA9555 in a reset
condition until VDD has reached VPOR. At that point, the reset condition is released and the
PCA9555 registers and SMBus state machine will initialize to their default states. The
power-on reset typically completes the reset and enables the part by the time the power
supply is above VPOR. However, when it is required to reset the part by lowering the power
supply, it is necessary to lower it below 0.2 V.
6.4 I/O port
When an I/O is congured as an input, FETs Q1 and Q2 are off, creating a
high-impedance input with a weak pull-up to VDD. The input voltage may be raised above
VDD to a maximum of 5.5 V.
If the I/O is congured as an output, then either Q1 or Q2 is on, depending on the state of
the Output Port register. Care should be exercised if an external voltage is applied to an
I/O congured as an output because of the low-impedance path that exists between the
pin and either VDD or VSS.
Table 11.
Conguration port 0 register
Bit
7
6
5
4
3
2
1
0
Symbol
C0.7
C0.6
C0.5
C0.4
C0.3
C0.2
C0.1
C0.0
Default
11111111
Table 12.
Conguration port 1 register
Bit
7
6
5
4
3
2
1
0
Symbol
C1.7
C1.6
C1.5
C1.4
C1.3
C1.2
C1.1
C1.0
Default
11111111
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