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參數(shù)資料
型號: PCA9555BS,118
廠商: NXP Semiconductors
文件頁數(shù): 3/34頁
文件大?。?/td> 0K
描述: IC I/O EXPANDER I2C 16B 24HVQFN
產品培訓模塊: I²C Bus Fundamentals
特色產品: NXP - I2C Interface
標準包裝: 1
接口: I²C,SM 總線
輸入/輸出數(shù): 16
中斷輸出:
頻率 - 時鐘: 400kHz
電源電壓: 2.3 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 24-VFQFN 裸露焊盤
供應商設備封裝: 24-HVQFN(4x4)
包裝: 標準包裝
包括: POR
產品目錄頁面: 826 (CN2011-ZH PDF)
配用: 568-4002-ND - DEMO BOARD I2C
其它名稱: 568-2382-6
PCA9555_8
NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 08 — 22 October 2009
11 of 34
NXP Semiconductors
PCA9555
16-bit I2C-bus and SMBus I/O port with interrupt
6.5.2 Reading the port registers
In order to read data from the PCA9555, the bus master must rst send the PCA9555
address with the least signicant bit set to a logic 0 (see Figure 8 “PCA9555 device
address”). The command byte is sent after the address and determines which register will
be accessed. After a restart, the device address is sent again, but this time the least
signicant bit is set to a logic 1. Data from the register dened by the command byte will
then be sent by the PCA9555 (see Figure 12, Figure 13 and Figure 14). Data is clocked
into the register on the falling edge of the acknowledge clock pulse. After the rst byte is
read, additional bytes may be read but the data will now reect the information in the other
register in the pair. For example, if you read Input Port 1, then the next byte read would be
Input Port 0. There is no limitation on the number of data bytes received in one read
transmission but the nal byte received, the bus master must not acknowledge the data.
Remark: Transfer can be stopped at any time by a STOP condition.
Fig 12. Read from register
A
S
START condition
R/W
acknowledge
from slave
002aac222
A
acknowledge
from slave
SDA
A
P
acknowledge
from master
DATA (first byte)
slave address
STOP
condition
S
(repeated)
START condition
(cont.)
1
0
A2 A1 A0
1
A
0
R/W
acknowledge
from slave
slave address
at this moment master-transmitter becomes master-receiver
and slave-receiver becomes slave-transmitter
NA
no acknowledge
from master
COMMAND BYTE
1
0
A2 A1 A0
0
data from lower or
upper byte of register
LSB
MSB
DATA (last byte)
data from upper or
lower byte of register
LSB
MSB
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