Philips Semiconductors
Product data
PCA9545
4-channel I
2
C switch with interrupt logic and reset
2002 Mar 28
5
853-2302 27311
INTERRUPT HANDLING
The PCA9545 provides 4 interrupt inputs, one for each channel, and
one open drain interrupt output. When an interrupt is generated by any
device, it will be detected by the PCA9545 and the interrupt output
will be driven LOW. The channel does not need to be active for
detection of the interrupt. A bit is also set in the control register.
Bits 4 – 7 of the control register correspond to channels 0 – 3 of the
PCA9545, respectively. Therefore, if an interrupt is generated by any
device connected to channel 1, the state of the interrupt inputs is
loaded into the control register when a read is accomplished.
Likewise, an interrupt on any device connected to channel 0 would
cause bit 4 of the control register to be set on the read. The master
can then address the PCA9545 and read the contents of the control
register to determine which channel contains the device generating the
interrupt. The master can then reconfigure the PCA9545 to select this
channel, and locate the device generating the interrupt and clear it.
It should be noted that more than one device can be providing an
interrupt on a channel, so it is up to the master to ensure that all
devices on a channel are interrogated for an interrupt.
The interrupt inputs may be used as general purpose inputs if the
interrupt function is not required.
If unused, interrupt input(s) must be connected to V
DD
through a
pull-up resistor.
Table 2. Control Register Read — Interrupt
INT3
INT2
INT1
INT0
B3
B2
B1
B0
COMMAND
No interrupt
on channel 0
Interrupt on
channel 0
No interrupt
on channel 1
Interrupt on
channel 1
No interrupt
on channel 2
Interrupt on
channel 2
No interrupt
on channel 3
Interrupt on
channel 3
X
X
X
0
X
X
X
X
1
X
X
0
X
X
X
X
X
1
X
0
X
X
X
X
X
X
1
0
X
X
X
X
X
X
X
1
NOTE:
Several interrupts can be active at the same time.
Ex: INT3 = 0, INT2 = 1, INT1 = 1, INT0 = 0, means that there is no
interrupt on channels 0 and 3, and there is interrupt on channels 1
and 2.
RESET INPUT
The RESET input is an active-LOW signal which may be used to
recover from a bus fault condition. By asserting this signal LOW for
a minimum of t
WL
, the PCA9545 will reset its registers and I
2
C state
machine and will deselect all channels. The RESET input must be
connected to V
DD
through a pull-up resistor.
POWER-ON RESET
When power is applied to V
DD
, an internal Power On Reset holds
the PCA9545 in a reset state until V
DD
has reached V
POR
. At this
point, the reset condition is released and the PCA9545 registers and
I
2
C state machine are initialized to their default states, all zeroes
causing all the channels to be deselected.
VOLTAGE TRANSLATION
The pass gate transistors of the PCA9545 are constructed such that
the V
DD
voltage can be used to limit the maximum voltage that will
be passed from one I
2
C bus to another.
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
V
pass
vs. V
DD
2.5
3.0
3.5
4.0
4.5
5.0
5.5
V
pass
V
DD
MINIMUM
TYPICAL
MAXIMUM
SW00820
2.0
Figure 5. V
pass
voltage vs. V
DD
Figure 5 shows the voltage characteristics of the pass gate
transistors (note that the graph was generated using the data
specified in the DC Characteristics section of this datasheet). In
order for the PCA9545 to act as a voltage translator, the V
pass
voltage should be equal to, or lower than the lowest bus voltage. For
example, if the main bus was running at 5 V, and the downstream
buses were 3.3 V and 2.7 V, then V
pass
should be equal to or below
2.7 V to effectively clamp the downstream bus voltages. Looking at
Figure 5, we see that V
pass
(max.) will be at 2.7 V when the
PCA9545 supply voltage is 3.5 V or lower so the PCA9545 supply
voltage could be set to 3.3 V. Pull-up resistors can then be used to
bring the bus voltages to their appropriate levels (see Figure 12).
More Information can be found in Application Note AN262 PCA954X
family of I
2
C/SMBus multiplexers and switches.