參數(shù)資料
型號: PCA9539RPW,118
廠商: NXP Semiconductors
文件頁數(shù): 13/37頁
文件大?。?/td> 0K
描述: IC I/O EXPANDER I2C 16B 24TSSOP
標準包裝: 2,500
接口: I²C,SM 總線
輸入/輸出數(shù): 16
中斷輸出:
頻率 - 時鐘: 400kHz
電源電壓: 2.3 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 24-TSSOP(0.173",4.40mm 寬)
供應商設備封裝: 24-TSSOP
包裝: 帶卷 (TR)
包括: POR
其它名稱: 935286605118
PCA9539RPW-T
PCA9539RPW-T-ND
PCA9539_PCA9539R
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 6 — 6 February 2013
20 of 37
NXP Semiconductors
PCA9539; PCA9539R
16-bit I2C-bus and SMBus low power I/O port with interrupt and reset
11. Dynamic characteristics
[1]
tVD;ACK = time for acknowledgement signal from SCL LOW to SDA (out) LOW.
[2]
tVD;DAT = minimum time for SDA data out to be valid following SCL LOW.
[3]
Cb = total capacitance of one bus line in pF.
[4]
tv(Q) measured from 0.7VDD on SCL to 50 % I/O output.
[5]
Resetting the device while actively communicating on the bus may cause glitches or errant STOP conditions.
[6]
Upon reset, the full delay will be the sum of trst and the RC time constant of the SDA bus.
Table 16.
Dynamic characteristics
Symbol
Parameter
Conditions
Standard-mode
I2C-bus
Fast-mode I2C-bus
Unit
Min
Max
Min
Max
fSCL
SCL clock frequency
0
100
0
400
kHz
tBUF
bus free time between a STOP and
START condition
4.7
-
1.3
-
s
tHD;STA
hold time (repeated) START condition
4.0
-
0.6
-
s
tSU;STA
set-up time for a repeated START
condition
4.7
-
0.6
-
s
tSU;STO
set-up time for STOP condition
4.0
-
0.6
-
s
tVD;ACK
data valid acknowledge time
0.3
3.45
0.1
0.9
s
tHD;DAT
data hold time
0
-
0
-
ns
tVD;DAT
data valid time
300
-
50
-
ns
tSU;DAT
data set-up time
250
-
100
-
ns
tLOW
LOW period of the SCL clock
4.7
-
1.3
-
s
tHIGH
HIGH period of the SCL clock
4.0
-
0.6
-
s
tf
fall time of both SDA and SCL signals
-300
20 + 0.1Cb
300
ns
tr
rise time of both SDA and SCL signals
-
1000
20 + 0.1Cb
300
ns
tSP
pulse width of spikes that must be
suppressed by the input filter
-
50
-
50
ns
Port timing
tv(Q)
data output valid time
-
200
-
200
ns
tsu(D)
data input set-up time
150
-
150
-
ns
th(D)
data input hold time
1
-
1
-
s
Interrupt timing
tv(INT_N)
valid time on pin INT
-4
-
4
s
trst(INT_N)
reset time on pin INT
-4
-
4
s
RESET timing
tw(rst)
reset pulse width
4
-
4
-
ns
trec(rst)
reset recovery time
0
-
0
-
ns
trst
reset time
400
-
400
-
ns
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