參數(shù)資料
型號： PCA9538PW,118
廠商： NXP Semiconductors
文件頁數(shù)： 33/34頁
文件大?。?/td> 0K
描述： IC I/O EXPANDER I2C 8B 16TSSOP
產(chǎn)品培訓(xùn)模塊： I²C Bus Fundamentals
特色產(chǎn)品： NXP - I2C Interface
標(biāo)準(zhǔn)包裝： 1
接口： I²C，SM 總線
輸入/輸出數(shù)： 8
中斷輸出： 是
頻率 - 時(shí)鐘： 400kHz
電源電壓： 2.3 V ~ 5.5 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 16-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 16-TSSOP
包裝： 標(biāo)準(zhǔn)包裝
包括： POR
產(chǎn)品目錄頁面： 825 (CN2011-ZH PDF)
配用： 568-3615-ND - DEMO BOARD I2C
其它名稱： 568-1840-6
PCA9538
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 6 — 6 February 2013
8 of 34
NXP Semiconductors
PCA9538
8-bit I2C-bus and SMBus low power I/O port with interrupt and reset
6.2.5 Register 3 - Configuration register
This register configures the directions of the I/O pins. If a bit in this register is set, the
corresponding port pin is enabled as an input with high-impedance output driver. If a bit in
this register is cleared, the corresponding port pin is enabled as an output. At reset, the
I/Os are configured as inputs.
6.3 Power-on reset
When power is applied to VDD, an internal Power-On Reset (POR) holds the PCA9538 in
a reset condition until VDD has reached VPOR. At that point, the reset condition is released
and the PCA9538 registers and state machine will initialize to their default states.
Thereafter, VDD must be lowered below 0.2 V to reset the device.
For a power reset cycle, VDD must be lowered below 0.2 V and then restored to the
operating voltage.
6.4 RESET input
A reset can be accomplished by holding the RESET pin LOW for a minimum of tw(rst).
The PCA9538 registers and SMBus/I2C-bus state machine will be held in their default
state until the RESET input is once again HIGH. This input requires a pull-up resistor to
VDD if no active connection is used.
6.5 Interrupt output
The open-drain interrupt output (INT) is activated when one of the port pins changes state
and the pin is configured as an input. The interrupt is de-activated when the input returns
to its previous state or the Input Port register is read.
Note that changing an I/O from an output to an input may cause a false interrupt to occur
if the state of the pin does not match the contents of the Input Port register.
Table 8.
Register 3 - Configuration register bit description
Legend: * default value.
Bit
Symbol
Access
Value
Description
7
C7
R/W
1*
configures the directions of the I/O pins
0 = corresponding port pin enabled as an output
1 = corresponding port pin configured as an input
(default value)
6C6
R/W
1*
5C5
R/W
1*
4C4
R/W
1*
3C3
R/W
1*
2C2
R/W
1*
1C1
R/W
1*
0C0
R/W
1*
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