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參數(shù)資料
型號: PCA9536TK,118
廠商: NXP Semiconductors
文件頁數(shù): 19/22頁
文件大?。?/td> 0K
描述: IC I/O EXPANDER I2C 4B 8HVSON
產(chǎn)品培訓(xùn)模塊: I²C Bus Fundamentals
特色產(chǎn)品: NXP - I2C Interface
標準包裝: 1
接口: I²C,SM 總線
輸入/輸出數(shù): 4
中斷輸出:
頻率 - 時鐘: 400kHz
電源電壓: 2.3 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 8-VFDFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 8-HVSON
包裝: 標準包裝
包括: POR
產(chǎn)品目錄頁面: 825 (CN2011-ZH PDF)
配用: 568-3615-ND - DEMO BOARD I2C
其它名稱: 568-4079-6
PCA9536_5
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 05 — 25 January 2010
6 of 22
NXP Semiconductors
PCA9536
4-bit I2C-bus and SMBus I/O port
6.1.5 Register 3 - Configuration register
This register configures the directions of the I/O pins. If a bit in this register is set, the
corresponding port pin is enabled as an input with high-impedance output driver. If a bit in
this register is cleared, the corresponding port pin is enabled as an output. At reset, the
I/Os are configured as inputs with a weak pull-up to VDD.
‘Not used’ bits can be programmed with either logic 0 or logic 1.
6.2 Power-on reset
When power is applied to VDD, an internal Power-On Reset (POR) holds the PCA9536 in
a reset condition until VDD has reached VPOR. At that point, the reset condition is released
and the PCA9536 registers and state machine will initialize to their default states.
Thereafter, VDD must be lowered below 0.2 V to reset the device.
For a power reset cycle, VDD must be lowered below 0.2 V and then restored to the
operating voltage.
6.3 I/O port
When an I/O is configured as an input, FETs Q1 and Q2 are off, creating a
high-impedance input with a weak pull-up (100 k
Ω typical) to V
DD. The input voltage may
be raised above VDD to a maximum of 5.5 V.
If the I/O is configured as an output, then either Q1 or Q2 is enabled, depending on the
state of the Output Port register. Care should be exercised if an external voltage is applied
to an I/O configured as an output because of the low-impedance paths that exist between
the pin and either VDD or VSS.
Table 7.
Register 3 - Configuration register bit description
Legend: * default value
Bit
Symbol
Access
Value
Description
7
C7
R/W
1*
not used
6C6
R/W
1*
5C5
R/W
1*
4C4
R/W
1*
3
C3
R/W
1*
configures the directions of the I/O pins
0 = corresponding port pin enabled as an output
1 = corresponding port pin configured as input
(default value)
2C2
R/W
1*
1C1
R/W
1*
0C0
R/W
1*
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