參數(shù)資料
型號: PCA9536
廠商: NXP Semiconductors N.V.
英文描述: 4-bit I2C and SMBus I/O port
中文描述: 4位I2C和SMBus I / O端口
文件頁數(shù): 11/16頁
文件大?。?/td> 153K
代理商: PCA9536
Philips Semiconductors
Objective data sheet
PCA9536
4-bit I
2
C and SMBus I/O port
2004 Aug 20
11
AC SPECIFICATIONS
SYMBOL
PARAMETER
STANDARD MODE
I
2
C-bus
MIN
0
FAST MODE
I
2
C-bus
MIN
0
UNITS
MAX
100
MAX
400
f
SCL
t
BUF
t
HD;STA
t
SU;STA
t
SU;STO
t
HD;DAT
t
VD;ACK
t
VD;DAT
t
SU;DAT
t
LOW
t
HIGH
t
F
t
R
t
SP
Operating frequency
kHz
μ
s
μ
s
μ
s
μ
s
ns
μ
s
ns
Bus free time between STOP and START conditions
4.7
1.3
Hold time after (repeated) START condition
4.0
0.6
Repeated START condition setup time
4.7
0.6
Setup time for STOP condition
4.0
0.6
Data in hold time
Valid time for ACK condition
2
Data out valid time
3
0
0
0.3
3.45
0.1
0.9
300
50
Data setup time
250
100
ns
μ
s
μ
s
ns
Clock LOW period
4.7
1.3
Clock HIGH period
4.0
0.6
Clock/Data fall time
300
20 + 0.1 C
b1
20 + 0.1 C
b1
300
Clock/Data rise time
1000
300
ns
Pulse width of spikes that must be suppressed by the
input filters
50
50
ns
Port Timing
t
PV
t
PS
t
PH
Output data valid
200
200
ns
Input data setup time
100
100
ns
μ
s
Input data hold time
1
1
NOTES:
1. C
b
= total capacitance of one bus line in pF.
2. t
VD;ACK
= time for Acknowledgement signal from SCL LOW to SDA (out) LOW.
3. t
VD;DAT
= minimum time for SDA data out to be valid following SCL LOW.
SDA
SCL
SU01469
t
HD;STA
t
F
S
t
LOW
t
R
t
HD;DAT
t
SU;DAT
t
HIGH
t
F
t
SU;STA
S
R
t
HD;STA
t
SP
t
SU;STD
P
t
R
t
BUF
S
Figure 10. Definition of timing
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