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參數(shù)資料
| 型號： | PCA9500PW,118 |
| 廠商： | NXP Semiconductors |
| 文件頁數(shù)： | 2/26頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC I/O EXPANDER I2C 8B 16TSSOP |
| 標準包裝： | 2,500 |
| 接口： | I²C，SM 總線 |
| 輸入/輸出數(shù)： | 8 |
| 中斷輸出： | 無 |
| 頻率 - 時鐘： | 400kHz |
| 電源電壓： | 2.5 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-TSSOP（0.173"，4.40mm 寬） |
| 供應商設(shè)備封裝： | 16-TSSOP |
| 包裝： | 帶卷 (TR) |
| 包括： | EEPROM，POR |
| 其它名稱： | 935271534118 PCA9500PW-T PCA9500PW-T-ND |
PCA9500_4
NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 15 April 2009
10 of 26
NXP Semiconductors
PCA9500
8-bit I2C-bus and SMBus I/O port with 2-kbit EEPROM
8.
Characteristics of the I2C-bus
The I2C-bus is for 2-way, 2-line communication between different ICs or modules. The two
lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be
connected to a positive supply via a pull-up resistor when connected to the output stages
of a device. Data transfer may be initiated only when the bus is not busy.
8.1 Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
will be interpreted as control signals (see Figure 15).
8.1.1 START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW
transition of the data line while the clock is HIGH is dened as the START condition (S).
A LOW-to-HIGH transition of the data line while the clock is HIGH is dened as the STOP
condition (P) (see Figure 16).
Fig 15. Bit transfer
mba607
data line
stable;
data valid
change
of data
allowed
SDA
SCL
Fig 16. Denition of START and STOP conditions
mba608
SDA
SCL
P
STOP condition
S
START condition
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