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參數(shù)資料
| 型號： | PCA8521FP |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 搖控器 |
| 英文描述： | Infrared remote control transmitter RC5 |
| 中文描述： | INFRARED, TRANSMITTER IC, PDIP16 |
| 封裝： | 0.300 INCH, PLASTIC, SOT-38-4, DIP-16 |
| 文件頁數(shù)： | 7/20頁 |
| 文件大?。?/td> | 100K |
| 代理商： | PCA8521FP |
1999 Jun 15
7
Philips Semiconductors
Product specification
Infrared remote control transmitter RC5
PCA8521
Timing generator
A schematic diagram of the timing generator is illustrated
in Fig.4. The oscillator frequency is 432 kHz or 4 MHz.
The timing generator is stopped when no key is activated
and started again when a key is pressed.
The output of the oscillator (CLK1) is divided by 111 for
4 MHz or by 12 for 432 kHz. Selection is achieved using a
mask option. The output of the divider is CLK2 which is
used for clocking of the control timer. The frequency of
CLK2 is 36 kHz and the inverse is used to generate the
output pulses in the subcarrier frequency. By mask option
the duty factor can be chosen to be 25% or 33%.
The control timer has a length of 4096 subcarrier (pulse)
periods. This is equal to the transmission repetition time.
A bit time is equal to 64 pulses and the repetition time is
64 bit times. The control timer provides the timing of the
key scanning, the ROM access and the code transmission.
When the control timer has arrived at a certain state, and
no key has been pressed for at least 28 ms, a stop signal
will be generated which will stop the oscillator. All drive
lines will then be set to logic 0. As soon as a key is pressed
one of the sense lines will become logic 0. This will
generate a start signal which will restart the oscillator.
Key scanning
Six bits of the control timer are used to control the key
scanning, subsequently 64 time slots are available. Each
time slot corresponds to a key number. The 3 most
significant bits (MSBs) control the drive lines and the
3 least significant bits (LSBs) control the sense lines.
The scan timing is illustrated in Fig.5. In the first 8 time
slots drive line DR0 is LOW. During this time the 8 sense
lines SN0 to SN7 are sequentially tested. The same
occurs for the next 8 time slots when DR1 is at logic 0 and
so on until DR6 is at logic 0. After testing there are 8 time
slots when no drive line is at logic 0 (all drive lines HIGH).
When, during time slots 0 to 63, one of the sense lines is
at logic 0 the contents of the 6 bits is stored in the key
register. This register is used to address the ROM.
No transmission will take place when two or more keys are
activated. This situation is considered to be the same as
‘no key’ and the control bit in the command word for the
next transmission will be toggled.
When no key is pressed the oscillator will stop at the end
of the control timer (see Section “Timing generator”).
In this situation all drive lines will be set to logic 0. When
one of the keys is pressed again a wake-up will occur by
starting the oscillator.
An option is available to select ‘single’ or ‘multi’ system.
Single system
SN0 should be connected to one of the drive lines or
ground.
The bank that will be selected is equal to drive line number
to which SN0 is connected. When connected to ground the
number will be 7. This is achieved by loading the bank
select flip-flops BS0 to BS2 with the contents of C5 to C7
of the control timer (see Fig.4) when sense line SN0 is at
logic 0. In this way it is possible to use two different
systems in one transmitter by using a side switch. With this
option SN0 cannot be used to connect keys, so the
maximum number of keys will be lower. (49 keys with
20-pin IC and 25 keys with 16-pin IC).
Multi system
The bank is selected by key for maximum 8 different
systems (e.g. TV, VCR, CD, etc.), any key is flexible for
bank selection. When a user inserts a new battery, the
default bank is always in bank 7. If only bank 7 is used,
then maximum number of keys can be:
56 keys for a 20-pin IC
30 keys for 16-pin IC.
ROM
A schematic diagram of the ROM is illustrated in Fig.6.
The ROM is divided into 8 banks of 2
×
64 bytes. Bank
selection is performed using flip-flops BS0 to BS2 that are
the 3 highest bits of the address. With the ‘single system’
these bits are loaded from the 3 MSBs of the scan control
when SN0 = 0. At power-on the bank select flip-flops will
be in an arbitrary state.
When a key was activated, the key number is stored in the
6-bit key register. This register forms the lower bits of the
ROM address. For each command the ROM will be
accessed twice. This gives 16 bits in total (M0L to M7L
and M0H to M7H). The bits are described in Table 3.
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