參數(shù)資料
型號(hào)： PCA8514P
廠商： NXP Semiconductors N.V.
英文描述： Stand-alone OSD
中文描述： 單機(jī)OSD
文件頁(yè)數(shù)： 7/64頁(yè)
文件大小： 322K
代理商： PCA8514P
1995 Nov 27
7
Philips Semiconductors
Product specification
Stand-alone OSD
PCA8514
6
SERIAL I/O
The PCA8514 has two means by which it can
communicate with a microcontroller: a fast I
2
C-bus serial
interface and a High-speed serial interface. Selection of
either interface is achieved via pin 15, HIO/I
2
C. When
HIO/I
2
C is LOW, the HIO serial interface is selected. When
HIO/I
2
C is HIGH, the I
2
C-bus serial interface is selected.
The PCA8514 is programmed by a series of commands
sent via one of these interfaces. There are 16 commands;
each command selecting different functions of the
PCA8514. The 16 commands are described in detail in
Chapter 9.
6.1
I
2
C-bus serial interface
The I
2
C-bus serial interface is selected by driving pin 15
(HIO/I
2
C) HIGH. Data transmission conforms to the fast
I
2
C-bus protocol; the maximum transmission rate being
400 kHz. The PCA8514 operates in the slave receiver
mode and therefore in normal operation is ‘write only’ from
the master device.
The format of the data streams sent via the I
2
C-bus
interface is shown in Fig.3. The first data byte is the slave
address 1011 101X
b
. The last bit of the slave address is
always a logic 0, except in the Test mode when it could be
a logic 1. Subsequent data bytes contain the commands
for control of the device. Upon the successful reception of
a complete data byte by the shift register, an Acknowledge
bit is sent. A STOP condition terminates the data transfer
operation.
The I
2
C-bus interface is reset to its initial state (waiting for
a slave address call) by the following conditions:
After a master reset
After a bus error has been detected on the I
2
C-bus
interface.
Under both these conditions the data held in the shift
register is abandoned.
6.1.1
M
AXIMUM SPEED OF THE
I
2
C-
BUS
The maximum I
2
C-bus transmission rate that the
PCA8514 can receive is 400 kHz. However, if the data
byte being transmitted is for display RAM then internal
synchronization of the write operation from the shift
register to the display RAM location is necessary. This will
reduce the maximum transmission speed.
The synchronization process is carried out by on-chip
hardware and takes place during the HSYNC retrace
period when VSYNC is inactive. The I
2
C-bus clock is
pulled LOW if a complete display RAM data byte is
received before HSYNC becomes active. The I
2
C-bus
clock will be released when HSYNC becomes active and
then the contents of the shift register will be written into the
display RAM location.
6.2
High-speed serial interface (HIO)
The High-speed serial interface is selected when pin 15
(HIO/I
2
C) is pulled LOW. The High-speed serial interface
has a 3-wire communication protocol; the maximum
transmission rate being 1 MHz. The interface protocol is
illustrated in Fig.4 and described below.
1.
Pin 14 (E) the chip enable pin is driven HIGH. This
LOW-to-HIGH transition clears the shift register and
resets the serial input circuit.
2.
On the first HIGH-to-LOW transition of SCLK after the
interface has been enabled, the first data bit (D0) must
be present at the SIN pin.
3.
On the following LOW-to-HIGH transition of SCLK, the
first data bit (D0) will be latched into the shift register.
4.
On the next HIGH-to-LOW transition of SCLK the
second data bit (D1) must be present at the SIN pin.
Data bit (D1) will be latched into the shift register on
the following LOW-to-HIGH transition of SCLK.
5.
The operation specified in step 4 above is repeated
another 6 times, thus loading the shift register with a
complete data byte. This data byte is then transferred
to the command interpreter which takes the
appropriate action.
6.
Providing the chip enable signal remains HIGH, a
2nd data byte can be transferred. The 1st data bit of
the next data transfer takes place on the falling edge
of the SCLK signal.
The following points should be noted:
If the chip enable signal is pulled LOW at any time the
shift operation in progress is stopped and the HIO slave
receiver is disabled
The rising edge of the chip enable signal resets the HIO
slave receiver.
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