1995 Nov 27
46
Philips Semiconductors
Product specification
Stand-alone OSD
PCA8514
11 OSD CLOCK
The on-chip clock generator comprises Phase-Locked
Loop circuitry and is shown in Fig.39. The frequency of the
OSD clock is programmable and is determined by the
contents of the 6-bit counter, which is loaded using
Command 6. The OSD clock frequency is calculated as
shown below; frequencies within the range 4 to 14 MHz
can be selected.
Where: 16 < (PLLCN) < 40; (PLLCN) is the decimal value
held in the 6-bit counter.
The Voltage Controlled Oscillator (VCO) is synchronized
to the HIGH-to-LOW edge of f
1
(see Fig.39) which is
always on the trailing edge of f
HSYNC
. The programmable
active level detector will pass the HSYNC signal if it is
programmed as active HIGH or invert the HSYNC signal if
it is programmed as active LOW. The 4-bit prescaler
increments or decrements the output of the VCO in steps
of (16
×
f
HSYNC
).
f
OSD
f
HSYNC
16
PLLCN
(
)
×
×
=
The OSD clock is enabled/disabled using Command 7;
see Section 9.8. When the OSD clock is disabled, the
oscillator remains active, therefore the transient time from
the OSD clock start-up to locking into the external H
SYNC
signal is reduced. As the on-chip oscillator is always active
after power-on, when the OSD clock is enabled no large
currents flow (as for RC or LC oscillators); therefore
radiated noise is dramatically reduced.
Character width is a function of the OSD clock frequency;
decreasing f
OSD
increases the width of the characters.
Therefore, for optimum character display quality the
choice of the OSD clock frequency is important; this is
explained in Chapter 12.
Fig.39 Block diagram of OSD oscillator.
handbook, full pagewidth
MLC349
VOLTAGE
CONTROLLED
OSCILLATOR
CHARGE PUMP
AND
LOOP FILTER
PHASE/
FREQUENCY
DETECTOR
ACTIVE
LEVEL
DETECTOR
PROGRAMMABLE
6-BIT COUNTER
fOSD
divided by N
4-BIT
PRESCALER
HSYNC
OSD disable
fPLL
f1
C
R1
C1