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參數(shù)資料
| 型號： | PCA2000 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 32 kHz watch circuit with programmable adaptive motor pulse |
| 中文描述： | 32千赫的可編程自適應(yīng)脈沖馬達手表電路 |
| 文件頁數(shù)： | 13/19頁 |
| 文件大小： | 120K |
| 代理商： | PCA2000 |
2003 Dec 17
13
Philips Semiconductors
Product specification
32 kHz watch circuit with programmable
adaptive motor pulse
PCA2000; PCA2001
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134).
Notes
1.
2.
For writing to the OTP cells, the supply voltage V
DD
can be raised to a maximum of 12 V for a period of 1 second.
Connecting the battery with reversed polarity does not destroy the circuit, but in this condition a large current flows,
which rapidly discharges the battery.
HANDLING
Inputs and outputs are protected against electrostatic discharges in normal handling. However to be totally safe, it is
advised to undertake handling precautions appropriate to handling MOS devices. Advice can be found in
“Data handbook IC16: General; handling MOS devices”
CHARACTERISTICS
V
DD
= 1.55 V; V
SS
= 0 V; f
osc
= 32.768 kHz; T
amb
= 25
°
C; quartz crystal: R
S
= 40 k
, C
1
= 2 to 3 fF, C
L
= 8.2 pF; unless
otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
V
DD
V
i
T
amb
T
stg
t
o(sc)
supply voltage
all input voltages
ambient temperature
storage temperature
output short-circuit duration
V
SS
= 0 V; notes 1 and 2
1.8
V
SS
0.5
10
30
+7.0
V
DD
+ 0.5
+60
+100
V
V
°
C
°
C
s
indefinite
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supply
V
DD
supply voltage
normal operating mode;
T
amb
=
10 to +60
°
C
V/
t = 1 V/
μ
s
between motor pulses
between motor pulses at V
DD
= 3.5 V
T
amb
=
10 to +60
°
C
stop mode; pad RESET connected to V
DD
1.10
1.55
3.60
V
V
DD
I
DD
supply voltage variation
supply current
90
120
100
0.25
120
180
200
135
V
nA
nA
nA
nA
Motor output
V
sat
Z
sc
Oscillator
saturation voltage
short-circuit impedance
R
M
= 2 k
; T
amb
=
10 to +60
°
C; note 1
between motor pulses; I
motor
< 1 mA
150
200
200
300
mV
V
start
g
m
t
osc
f/f
C
int
R
par
starting voltage
transconductance
start-up time
frequency stability
integrated load capacitance
parasitic resistance
5
4.3
10
0.3
0.05
5.2
0.9
0.20
6.3
V
μ
S
s
ppm
pF
M
V
OSCIN
≤
50 mV (p-p)
V
DD
= 100 mV
allowed resistance between adjacent pads 20
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