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參數(shù)資料
| 型號(hào)： | PC87308 |
| 文件頁數(shù)： | 3/6頁 |
| 文件大?。?/td> | 110K |
| 代理商： | PC87308 |
Features
(Continued)
Y
A bidirectional parallel port that includes:
D A modifiable address that is referenced by a 16-bit
programmable register
D Software or hardware control
D 13 IRQ channel options
D Four 8-bit DMA channel options
D Demand mode DMA support
D An Enhanced Parallel Port (EPP) that is compatible
with the new version EPP 1.9, and is IEEE 1284
compliant
D An Enhanced Parallel Port (EPP) that also supports
version EPP 1.7 of the Xircom specification.
D Support for an Enhanced Parallel Port (EPP) as
mode 4 of the Extended Capabilities Port (ECP)
D An Extended Capabilities Port (ECP) that is IEEE
1284 compliant, including level 2
D Selection of internal pull-up or pull-down resistor for
Paper End (PE) pin
D Reduction of PCI bus utilization by supporting a de-
mand DMA mode mechanism and a DMA fairness
mechanism
D A protection circuit that prevents damage to the par-
allel port when a printer connected to it powers up
or is operated at high voltages
D Output buffers that can sink and source 14 mA
Y
Three general purpose pins for three separate program-
mable chip select signals, as follows:
D Can be programmed for game port control
D The Chip Select 0 (CS0) signal produces open drain
output and is powered by the V
CCH
D The Chip Select 1 (CS1) and 2 (CS2) signals have
push-pull buffers and are powered by the main V
DD
D Decoding of chip select signals depends on the ad-
dress and the Address Enable (AEN) signals, and
can be qualified using the Read (RD) and Write
(WR) signals.
Y
16 Single-Bit General Purpose I/O ports (GPIO):
D Modifiable addresses that are referenced by a 16-bit
programmable reigster
D Programmable direction for each signal (input or out-
put)
D Programmable drive type for each output pin (open-
drain or push-pull)
D Programmable option for internal pull-up resistor on
each input pin
D A back-drive protection circuit
Y
An X-bus data buffer that connects the 8-bit X data bus
to the ISA data bus
Y
Clock source options:
D Source is a 32.768 kHz crystal-an internal frequency
multiplier generates all the required internal frequen-
cies
D Source may be either a 48 MHz or 24 MHz clock in-
put signal
Y
Non-Volatile Memory (NVM) support via the Chip Select
0 (CS0) signal that is powered by the V
CCH
Y
Enhanced Power Management, including:
D Special configuration registers for power down
D Reduced current leakage from pins
D Low-power CMOS technology
D Ability to shut off clocks to all modules
Y
General features include:
D All accesses to the SuperI/O chip activate a Zero
Wait State (ZWS) signal, except for accesses to the
Enhanced Parallel Port (EPP) and to configuration
registers
D Access to all configuration registers is through an In-
dex and a Data register, which can be relocated
within the ISA I/O address space
D 160-pin Plastic Quad Flatpack (PQFP) package
http://www.national.com
3
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PC87308VUL | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:SuperI/O Enhanced Sidewinder Plug and Play Compatible Chip |
| PC87309 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:PC87309 SuperI/O Plug and Play Compatible Chip in Compact 100-Pin VLJ Packaging |
| PC87309VLJ | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:PC87309 SuperI/O Plug and Play Compatible Chip in Compact 100-Pin VLJ Packaging |
| PC87310 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:PC87310 (SuperI/OTM) Dual UART with Floppy Disk Controller and Parallel Port |
| PC87310EB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Floppy Disk Controller |
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