參數(shù)資料
型號(hào)： PC7447VGH933N
廠商： Atmel Corp.
英文描述： PowerPC 7457 RISC Microprocessor
中文描述： 7457的PowerPC RISC微處理器
文件頁(yè)數(shù)： 24/66頁(yè)
文件大?。?/td> 522K
代理商： PC7447VGH933N
24
PC7457/47 [Preliminary]
5345B–HIREL–02/04
Figure 10 provides the input/output timing diagram for the PC7457.
Figure 10.
Input/Output Timing Diagram
Note:
VM = Midpoint Voltage (OV
DD
/2)
L3 Clock AC Specifications
The L3_CLK frequency is programmed by the L3 configuration register core-to-L3 divi-
sor ratio. See Table 18 on page 51 for example core and L3 frequencies at various
divisors. Table 10 on page 25 provides the potential range of L3_CLK output AC timing
specifications as defined in Figure 11 on page 25.
The maximum L3_CLK frequency is the core frequency divided by two. Given the high
core frequencies available in the PC7457, however, most SRAM designs will be not be
able to operate in this mode using current technology and, as a result, will select a
greater core-to-L3 divisor to provide a longer L3_CLK period for read and write access
to the L3 SRAMs. Therefore, the typical L3_CLK frequency shown in Table 10 is consid-
ered to be the practical maximum in a typical system. The maximum L3_CLK frequency
for any application of the PC7457 will be a function of the AC timings of the PC7457, the
AC timings for the SRAM, bus loading, and printed-circuit board trace length, and may
be greater or less than the value given in Table 10. Note that SYSCLK input jitter and
L3_CLK[0:1] output jitter are already comprehended in the L3 bus AC timing specifica-
tions and do not need to be separately accounted for in an L3 AC timing analysis. Clock
skews, where applicable, do need to be accounted for in an AC timing analysis.
SYSCLK
All Inputs
VM
All Outputs
(Except TS,
VM
All Outputs
(Except TS,
TS
VM
tKHOE
ARTRY, SHD0, SHD1)
ARTRY, SHD0, SHD1)
ARTRY,
SHD0,
SHD1
tAVKH
tKHAV
tIVKH
tAXKH
tIXKH
tKHDV
tKHOV
tKHAX
tKHDX
tKHOX
tKHOZ
tKHTSPZ
tKHTSX
tKHTSV
tKHTSV
tKHARV
tKHARP
tKHARX
tKHARPZ
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