
Chapter 2 Port Integration Module (S12XEPIMV1)
MC9S12XE-Family Reference Manual , Rev. 1.07
170
Freescale Semiconductor
NOTE
Due to internal synchronization circuits, it can take up to 2 bus clock cycles
until the correct value is read on PTF or PTIF registers, when changing the
DDRF register.
2.3.104 Port F Reduced Drive Register (RDRF)
Table 2-97. DDRF Register Field Descriptions
Field
Description
7-0
DDRF
Port F data direction
—
This register controls the data direction of pins 7 through 0.This register configures each Port F pin as either input
or output.
If SPI0 is enabled, the SPI0 determines the pin direction.
Refer to SPI section for details
.
If the associated SCI transmit or receive channel is enabled this register has no effect on the pins. The pin is forced
to be an output if a SCI transmit channel is enabled, it is forced to be an input if the SCI receive channel is enabled.
The data direction bits revert to controlling the I/O direction of a pin when the associated channel is disabled.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
Address 0x037B
Access: User read/write
1
1
Read: Anytime.
Write: Anytime.
7
6
5
4
3
2
1
0
R
RDRF7
RDRF6
RDRF5
RDRF4
RDRF3
RDRF2
RDRF1
RDRF0
W
Reset
0
0
0
0
0
0
0
0
Figure 2-102. Port F Reduced Drive Register (RDRF)
Table 2-98. RDRF Register Field Descriptions
Field
Description
7-0
RDRF
Port F reduced drive
—Select reduced drive for outputs
This register configures the drive strength of output pins 7 through 0 as either full or reduced. If a pin is used as input
this bit has no effect.
1 Reduced drive selected (1/6 of the full drive strength).
0 Full drive strength enabled.