
Chapter 12 Serial Peripheral Interface (S12SPIV4)
MC9S12XDP512 Data Sheet, Rev. 2.17
516
Freescale Semiconductor
SPI operation in wait mode is a configurable low power mode, controlled by the SPISWAI bit
located in the SPICR2 register. In wait mode, if the SPISWAI bit is clear, the SPI operates like in
runmode.IftheSPISWAIbitisset,theSPIgoesintoapowerconservativestate,withtheSPIclock
generation turned off. If the SPI is configured as a master, any transmission in progress stops, but
is resumed after CPU goes into run mode. If the SPI is configured as a slave, reception and
transmission of a byte continues, so that the slave stays synchronized to the master.
Stop mode
The SPI is inactive in stop mode for reduced power consumption. If the SPI is configured as a
master,anytransmissioninprogressstops,butisresumedafterCPUgoesintorunmode.IftheSPI
is configured as a slave, reception and transmission of a byte continues, so that the slave stays
synchronized to the master.
This is a high level description only, detailed descriptions of operating modes are contained in
Section 12.4.7, “Low Power Mode Options”
.
12.1.4
Block Diagram
Figure 12-1
gives an overview on the SPI architecture. The main parts of the SPI are status, control and
data registers, shifter logic, baud rate generator, master/slave control logic, and port control logic.