
Chapter 11 Serial Communication Interface (S12SCIV5)
MC9S12XDP512 Data Sheet, Rev. 2.17
502
Freescale Semiconductor
11.4.6
Receiver
Figure 11-20. SCI Receiver Block Diagram
11.4.6.1
Receiver Character Length
The SCI receiver can accommodate either 8-bit or 9-bit data characters. The state of the M bit in SCI
control register 1 (SCICR1) determines the length of data characters. When receiving 9-bit data, bit R8 in
SCI data register high (SCIDRH) is the ninth bit (bit 8).
11.4.6.2
Character Reception
DuringanSCIreception,thereceiveshiftregistershiftsaframeinfromtheRXDpin.TheSCIdataregister
is the read-only buffer between the internal data bus and the receive shift register.
After a complete frame shifts into the receive shift register, the data portion of the frame transfers to the
SCI data register. The receive data register full flag, RDRF, in SCI status register 1 (SCISR1) becomes set,
A
M
WAKE
ILT
PE
PT
RE
H
8
7
6
5
4
3
2
1
0
L
11-Bit Receive Shift Register
S
S
Data
Recovery
Wakeup
Logic
Parity
Checking
M
SCI Data Register
R8
ILIE
RWU
RDRF
OR
NF
FE
PE
Internal Bus
Bus
Clock
SBR12:SBR0
Baud Divider
IDLE
RAF
RXPOL
LOOPS
Loop
Control
RSRC
SCRXD
From TXD Pin
or Transmitter
Idle IRQ
RDRF/OR
IRQ
Break
Detect Logic
Active Edge
Detect Logic
BRKDFE
BRKDIE
BRKDIF
RXEDGIE
RXEDGIF
Break IRQ
RX Active Edge IRQ
RIE