
Chapter 23 DQ256 Port Integration Module (S12XDQ256PIMV2)
MC9S12XDP512 Data Sheet, Rev. 2.17
918
Freescale Semiconductor
PTIP
R
W
PTIP7
PTIP6
PTIP5
PTIP4
PTIP3
PTIP2
PTIP1
PTIP0
DDRP
R
W
DDRP7
DDRP6
DDRP5
DDRP4
DDRP3
DDRP2
DDRP1
DDRP0
RDRP
R
W
RDRP7
RDRP6
RDRP5
RDRP4
RDRP3
RDRP2
RDRP1
RDRP0
PERP
R
W
PERP7
PERP6
PERP5
PERP4
PERP3
PERP2
PERP1
PERP0
PPSP
R
W
PPSP7
PPSP6
PPSP5
PPSP4
PPSP3
PPSP2
PPSP1
PPSP0
PIEP
R
W
PIEP7
PIEP6
PIEP5
PIEP4
PIEP3
PIEP2
PIEP1
PIEP0
PIFP
R
W
PIFP7
PIFP6
PIFP5
PIFP4
PIFP3
PIFP2
PIFP1
PIFP0
PTH
R
W
PTH7
PTH6
PTH5
PTH4
PTH3
PTH2
PTH1
PTH0
PTIH
R
W
PTIH7
PTIH6
PTIH5
PTIH4
PTIH3
PTIH2
PTIH1
PTIH0
DDRH
R
W
DDRH7
DDRH6
DDRH5
DDRH4
DDRH3
DDRH2
DDRH1
DDRH0
RDRH
R
W
RDRH7
RDRH6
RDRH5
RDRH4
RDRH3
RDRH2
RDRH1
RDRH0
PERH
R
W
PERH7
PERH6
PERH5
PERH4
PERH3
PERH2
PERH1
PERH0
PPSH
R
W
PPSH7
PPSH6
PPSH5
PPSH4
PPSH3
PPSH2
PPSH1
PPSH0
PIEH
R
W
PIEH7
PIEH6
PIEH5
PIEH4
PIEH3
PIEH2
PIEH1
PIEH0
PIFH
R
W
PIFH7
PIFH6
PIFH5
PIFH4
PIFH3
PIFH2
PIFH1
PIFH0
Register
Name
Bit 7
6
5
4
3
2
1
Bit 0
= Unimplemented or Reserved
Figure 23-2. PIM Register Summary (Sheet 5 of 7)