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Chapter 24 DG128 Port Integration Module (S12XDG128PIMV2)
MC9S12XDP512 Data Sheet, Rev. 2.17
988
Freescale Semiconductor
Non-PIM
Address
Range
R
W
Non-PIM Address Range
PORTK
R
W
PK7
0
PK5
PK4
PK3
PK2
PK1
PK0
DDRK
R
W
DDRK7
0
DDRK5
DDRK4
DDRK3
DDRK2
DDRK1
DDRK0
Non-PIM
Address
Range
R
W
Non-PIM Address Range
PTT
R
W
PTT7
PTT6
PTT5
PTT4
PTT3
PTT2
PTT1
PTT0
PTIT
R
W
PTIT7
PTIT6
PTIT5
PTIT4
PTIT3
PTIT2
PTIT1
PTIT0
DDRT
R
W
DDRT7
DDRT6
DDRT5
DDRT4
DDRT3
DDRT2
DDRT1
DDRT0
RDRT
R
W
RDRT7
RDRT6
RDRT5
RDRT4
RDRT3
RDRT2
RDRT1
RDRT0
PERT
R
W
PERT7
PERT6
PERT5
PERT4
PERT3
PERT2
PERT1
PERT0
PPST
R
W
PPST7
PPST6
PPST5
PPST4
PPST3
PPST2
PPST1
PPST0
Reserved
R
W
0
0
0
0
0
0
0
0
Reserved
R
W
0
0
0
0
0
0
0
0
PTS
R
W
PTS7
PTS6
PTS5
PTS4
PTS3
PTS2
PTS1
PTS0
PTIS
R
W
PTIS7
PTIS6
PTIS5
PTIS4
PTIS3
PTIS2
PTIS1
PTIS0
Register
Name
Bit 7
6
5
4
3
2
1
Bit 0
= Unimplemented or Reserved
Figure 24-2. PIM Register Summary (Sheet 3 of 7)