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    • 參數(shù)資料
    型號(hào)： PC28F640J3C-120
    廠商： Intel Corp.
    英文描述： Intel StrataFlash Memory (J3)
    中文描述： 英特爾StrataFlash存儲(chǔ)器（J3）
    文件頁(yè)數(shù)： 31/72頁(yè)
    文件大?。?/td> 905K
    代理商： PC28F640J3C-120
    256-Mbit J3 (x8/x16)
    Datasheet
    31
    8.0
    Power and Reset Specifications
    This section provides an overview of system level considerations for the Intel StrataFlash
    memory family device. This section provides a brief description of power-up, power-down,
    decoupling and reset design considerations.
    8.1
    Power-Up/Down Characteristics
    In order to prevent any condition that may result in a spurious write or erase operation, it is
    recommended to power-up and power-down VCC and VCCQ together. It is also recommended to
    power-up VPEN with or slightly after VCC. Conversely, VPEN must power down with or slightly
    before VCC.
    8.2
    Power Supply Decoupling
    When the device is enabled, many internal conditions change. Circuits are energized, charge pumps
    are switched on, and internal voltage nodes are ramped. All of this internal activities produce
    transient signals. The magnitude of the transient signals depends on the device and system loading.
    To minimize the effect of these transient signals, a 0.1 μF ceramic capacitor is required across each
    VCC/VSS and VCCQ
    signal
    . Capacitors should be placed as close as possible to device
    connections.
    Additionally, for every eight flash devices, a 4.7 μF electrolytic capacitor should be placed between
    VCC and VSS at the power supply connection. This 4.7 μF capacitor should help overcome
    voltage slumps caused by PCB (printed circuit board) trace inductance.
    8.3
    Reset Characteristics
    By holding the flash device in reset during power-up and power-down transitions, invalid bus
    conditions may be masked. The flash device enters reset mode when RP# is driven low. In reset,
    internal flash circuitry is disabled and outputs are placed in a high-impedance state. After return
    from reset, a certain amount of time is required before the flash device is able to perform normal
    operations. After return from reset, the flash device defaults to asynchronous page mode. If RP# is
    driven low during a program or erase operation, the program or erase operation will be aborted and
    the memory contents at the aborted block or address are no longer valid. See
    Figure 14, “AC
    Waveform for Reset Operation” on page 29
    for detailed information regarding reset timings.
    相關(guān)PDF資料
    PDF描述
    PC28F256J3C-115 Intel StrataFlash Memory (J3)
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    PC28F640J3C-115 Intel StrataFlash Memory (J3)
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    PC28F128J3C-120 Intel StrataFlash Memory (J3)
    相關(guān)代理商/技術(shù)參數(shù)
    參數(shù)描述
    PC28F640J3C-125 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel StrataFlash Memory (J3)
    PC28F640J3C-150 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel StrataFlash Memory (J3)
    PC28F640J3D75 制造商:Intel 功能描述:
    PC28F640J3D-75 制造商:Intel 功能描述:NOR Flash, 4M x 16, 64 Pin, Plastic, BGA
    PC28F640J3D75A 功能描述:IC FLASH 64MBIT 75NS 64EZBGA RoHS:是 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:StrataFlash™ 產(chǎn)品變化通告:Product Discontinuation 26/Apr/2010 標(biāo)準(zhǔn)包裝:136 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類型:SRAM - 同步，DDR II 存儲(chǔ)容量:18M（1M x 18） 速度:200MHz 接口:并聯(lián) 電源電壓:1.7 V ~ 1.9 V 工作溫度:0°C ~ 70°C 封裝/外殼:165-TBGA 供應(yīng)商設(shè)備封裝:165-CABGA（13x15） 包裝:托盤 其它名稱:71P71804S200BQ
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