參數(shù)資料
型號(hào)： PC2119SU
廠商： NXP Semiconductors N.V.
英文描述： KPTC 18C 18#20 PIN PLUG
中文描述： LCD控制器/驅(qū)動(dòng)器
文件頁(yè)數(shù)： 38/60頁(yè)
文件大?。?/td> 260K
代理商： PC2119SU
1999 Mar 02
38
Philips Semiconductors
Product specification
LCD controllers/drivers
PCF2119x
14 AC CHARACTERISTICS
V
DD
= 2.2 to 5.5 V; V
SS
= 0 V; V
LCD
= 2.2 to 6.5 V; T
amb
=
40 to +85
°
C; unless otherwise specified.
Note
1.
All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to
V
IL
and V
IH
with an input voltage swing of V
SS
to V
DD
.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
f
FR
f
OSC
f
OSC(ext)
t
OSCST
LCD frame frequency (internal clock)
oscillator frequency (not available at any pad)
external clock frequency
oscillator start-up time after power-down
V
DD
= 5.0 V
45
140
140
95
250
200
147
450
450
300
Hz
kHz
kHz
μ
s
Bus timing characteristics: parallel interface;
note 1
W
RITE OPERATION
(
WRITING DATA FROM
MPU
TO
PCF2119
X
)
T
cy(en)
t
W(en)
t
su(A)
t
h(A)
t
su(D)
t
h(D)
R
EAD OPERATION
(
READING DATA FROM
PCF2119
X TO
MPU)
enable cycle time
enable pulse width
address set-up time
address hold time
data set-up time
data hold time
500
220
50
25
60
25
ns
ns
ns
ns
ns
ns
T
cy(en)
t
W(en)
t
su(A)
t
h(A)
t
d(D)
t
h(D)
enable cycle time
enable pulse width
address set-up time
address hold time
data delay time
data hold time
500
220
50
25
20
150
100
ns
ns
ns
ns
ns
ns
Timing characteristics: I
2
C-bus interface;
note 1
f
SCL
t
LOW
t
HIGH
t
SU;DAT
t
HD;DAT
t
r
t
f
C
B
t
SU;STA
t
HD;STA
t
SU;STO
t
SW
SCL clock frequency
SCL clock low period
SCL clock high period
data set-up time
data hold time
SCL, SDA rise time
SCL, SDA fall time
capacitive bus line load
set-up time for a repeated START condition
START condition hold time
set-up time for STOP condition
tolerable spike width on bus
1.3
0.6
100
0
0.6
0.6
0.6
400
300
300
400
50
kHz
μ
s
μ
s
ns
ns
ns
ns
pF
μ
s
μ
s
μ
s
ns
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