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參數(shù)資料
| 型號： | PC107AVZFU100L |
| 廠商： | Atmel Corp. |
| 英文描述： | PCI Bridge Memory Controller |
| 中文描述： | PCI橋內(nèi)存控制器 |
| 文件頁數(shù)： | 23/50頁 |
| 文件大?。?/td> | 453K |
| 代理商： | PC107AVZFU100L |
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23
PC107A [Preliminary]
2137C–HIREL–03/04
Dynamic Electrical
Characteristics
Clock AC Specifications
Table 9 provides the clock AC timing specifications as defined in Section.
At recommended operating conditions (see Table 3 on page 12) with GV
DD
= 3.3V
±
5%
and LV
DD
= 3.3
±
0.3V
Notes:
1. These specifications are for the default driver strengths indicated in Table 8 on page 22.
2. Rise and fall times for the PCI_SYNC_IN input are measured from 0.4V to 2.4V.
3. Specification value at maximum frequency of operation.
4. Relock time is guaranteed by design and characterization. Relock time is not tested.
5. Rise and fall times for the OSC_IN input is guaranteed by design and characterization. OSC_IN input rise and fall times are
not tested.
6. Relock timing is guaranteed by design. PLL-relock time is the maximum amount of time required for PLL lock after a stable
V
DD
and PCI_SYNC_IN are reached during the reset sequence. This specification also applies when the PLL has been dis-
abled and subsequently re-enabled during sleep mode. Also note that HRESET must be held asserted for a minimum of 255
bus clocks after the PLL-relock time during the reset sequence.
7. DLL_STANDARD is bit 7 of the PMC2 register <72>. N is a non-zero integer (1 or 2). T
clk
is the period of one
SDRAM_SYNC_OUT clock cycle in ns. t
loop
is the propagation delay of the DLL synchronization feedback loop (PC board
runner) from SDRAM_SYNC_OUT to SDRAM_SYNC_IN in ns; 6.25 inches of loop length (unloaded PC board runner) cor-
responds to approximately 1 ns of delay. See Figure 12 on page 25 for DLL locking ranges.
8. See Table 19 on page 41 for PCI_SYNC_IN input frequency range for specific PLL_CFG[0–3] settings.
Table 9.
Clock AC Timing Specifications
Num
Characteristics and Conditions
(1)
Min
Max
Unit
Notes
1a
Frequency of Operation (PCI_SYNC_IN)
12.5
66
MHz
(8)
1b
PCI_SYNC_IN Cycle Time
80
15
ns
(8)
2, 3
PCI_SYNC_IN Rise and Fall Times
–
2.0
ns
(2)
4
PCI_SYNC_IN Duty Cycle Measured at 1.4V
40
60
%
5a
PCI_SYNC_IN Pulse Width High Measured at 1.4V
6
9
ns
(3)
5b
PCI_SYNC_IN Pulse Width Low Measured at 1.4V
6
9
ns
(3)
7
PCI_SYNC_IN Jitter
–
< 150
ps
9a
PCI_CLK[0–4] Skew (Pin to Pin)
–
500
ps
9b
SDRAM_CLK[0–3] Skew (Pin to Pin)
–
350
ps
9c
CPU_CLK[0–2] Skew (Pin to Pin)
–
350
ps
9d
SDRAM_CLK[0–3]/CPU_CLK[0–2] Jitter
–
150
ps
10
Internal PLL Relock Time
–
100
μs
(3)(4)(6)
15
DLL lock range with DLL_STANDARD = 1 (default)
See Figure 11 on page 24
ns
(7)
16
DLL lock range with DLL_STANDARD = 0
See Figure 12 on page 25
ns
(7)
17
Frequency of Operation (OSC_IN)
12.5
66
MHz
(8)
18
OSC_IN Cycle Time
80
15
ns
(8)
19
OSC_IN Rise and Fall Times
–
5
ns
(5)
20
OSC_IN Duty Cycle Measured at 1.4V
40
60
%
21
OSC_IN Frequency Stability
–
100
ppm
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PC107AVZFU100LC | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:PCI Bridge Memory Controller |
| PC107AVZFU100LD | 制造商:e2v technologies 功能描述:IC BRIDGE MEM CTRL 100 MHZ - Trays |
| PC107B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
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