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參數(shù)資料
| 型號： | PALLV22V10-15JI |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | PLD |
| 英文描述： | Low-Voltage Zero Power 24-Pin EE CMOS Versatile PAL Device |
| 中文描述： | EE PLD, 15 ns, PQCC28 |
| 封裝： | PLASTIC, LCC-28 |
| 文件頁數(shù)： | 1/19頁 |
| 文件大?。?/td> | 380K |
| 代理商： | PALLV22V10-15JI |
Publication# 18956
Rev: F
Amendment/0
Issue Date: September 2000
USE
GAL
DEVICES
FOR
NEW
DESIGNS
IND: -25
PALLV22V10 and PALLV22V10Z Families
Low-Voltage (Zero Power) 24-Pin EE CMOS
Versatile PAL Device
DISTINCTIVE CHARACTERISTICS
x
Low-voltage operation, 3.3 V JEDEC compatible
—VCC = + 3.0 V to 3.6 V
x
Commercial and industrial operating temperature range
x
7.5-ns tPD
x
Electrically-erasable technology provides recongurable logic and full testability
x
10 macrocells programmable as registered or combinatorial, and active high or active low to
match application needs
x
Varied product term distribution allows up to 16 product terms per output for complex
functions
x
Global asynchronous reset and synchronous preset for initialization
x
Power-up reset for initialization and register preload for testability
x
Extensive third-party software and programmer support
x
24-pin SKINNY DIP and 28-pin PLCC packages save space
GENERAL DESCRIPTION
The PALLV22V10 is an advanced PAL device built with low-voltage, high-speed, electrically-
erasable CMOS technology.
The PALLV22V10Z provides low voltage and zero standby power. At 30 A maximum standby
current, the PALLV22V10Z allows battery powered operation for an extended period.
The PALLV22V10 device implements the familiar Boolean logic transfer function, the sum of
products. The PAL device is a programmable AND array driving a xed OR array. The AND array
is programmed to create custom product terms, while the OR array sums selected terms at the
outputs.
The product terms are connected to the xed OR array with a varied distribution from 8 to 16
across the outputs (see Block Diagram). The OR sum of the products feeds the output macrocell.
Each macrocell can be programmed as registered or combinatorial, and active high or active low.
The output conguration is determined by two bits controlling two multiplexers in each macrocell.
COM'L: -7/10/15
IND: -15
PALLV22V10
PALLV22V10Z
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PALLV22V10-15PC | Header Connector,PCB Mnt,RECEPT,5 Contacts,PIN,0.1 Pitch,PC TAIL Terminal,LOCKING MECH |
| PALLV22V10-7JC | Low-Voltage Zero Power 24-Pin EE CMOS Versatile PAL Device |
| PLSI1032E-70LJ | High-Density Programmable Logic |
| PLSI1032E-80LJ | High-Density Programmable Logic |
| PLSI1032E-90LJ | COUPLING |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PALLV22V10-15PC | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:Low-Voltage Zero Power 24-Pin EE CMOS Versatile PAL Device |
| PALLV22V10-7JC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| PALLV22V10Z-25JI | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| PALLV22V10Z-25PI | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:Low-Voltage Zero Power 24-Pin EE CMOS Versatile PAL Device |
| PALLV22V10Z25SI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC |
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