- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄378032 > PACDT (California Micro Devices Corporation) P/Active 1% Tolerance Dual Thevenin Termination Network PDF資料下載
參數(shù)資料
| 型號(hào)： | PACDT |
| 廠商： | California Micro Devices Corporation |
| 英文描述： | P/Active 1% Tolerance Dual Thevenin Termination Network |
| 中文描述： | P /主動(dòng)1％誤差雙戴維南終端網(wǎng)絡(luò) |
| 文件頁數(shù)： | 1/2頁 |
| 文件大?。?/td> | 50K |
| 代理商： | PACDT |
CALIFORNIA MICRO DEVICES
2000 California Micro Devices Corp. All rights reserved.
11/19/2000
1
215 Topaz Street, Milpitas, California 95035
Tel: (408) 263-3214 Fax: (408) 263-7846 www.calmicro.com
PACDT
P/Active 1% Tolerance Dual Thévenin Termination Network
Features
Minimal ground bounce, crosstalk
Stable 1% absolute tolerance elements
16 terminating lines per QSOP package
Saves board space and reduces assembly cost
Product Description
High speed logic devices like HSTL (High Speed
Transceiver Logic) demand unique, high speed bus
terminations. The dual Thévenin termination network
provides 16 terminating channels per package, and
optimizes signal integrity by reducing reflections and
ringing. The terminations are available in a range of
standard values and are ideal for use in HSTL busses.
As seen in the schematic, R1 is typically tied to V
and
serves as a pull-up resistor, while R2 functions as a pull-
down resistor and is tied to ground (or the most negative
supply voltage). In addition, the equivalent Thévenin
Applications
HSTL termination
Thévenin termination
ECL, TTL termination
C1611100
resistance (R1 in parallel with R2) should match the
impedance of the trace. Ground-bounce and crosstalk
are virtually eliminated using a proprietary lead-frame
which includes four direct ground connections to the die
substrate, as well as four double-bonded connections to
V
, for a total of 8 commons. In addition, the resistors
are trimmed to a tight absolute tolerance of 1% which
provides tight impedance-matching and results in greatly
reduced reflections. This unique proprietary design
provides optimal signal integrity.
SCHEMATIC CONFIGURATION
V
CC
24
1
2
3
4
23
22
21
17
20
19
18
16
15
14
13
6
5
7
8
9
11
10
12
GND
47
50
56
68
94
100
112
136
94
100
112
136
001
002
003
004
CODE
R2 (
)
R1(
)
BUS IMPEDANCE (
)
STANDARD PART ORDERING INFORMATION
Package
Pin
Style
24
QSOP
PAC001DTFQ/T
24
QSOP
PAC002DTFQ/T
24
QSOP
PAC003DTFQ/T
24
QSOP
PAC004DTFQ/T
Ordering Part Number
Tubes
R Code
001
002
003
004
Tape & Reel
PAC001DTFQ/R
PAC002DTFQ/R
PAC003DTFQ/R
PAC004DTFQ/R
Part Marking
PAC001DTFQ
PAC002DTFQ
PAC003DTFQ
PAC004DTFQ
STANDARD VALUES
Absolute Tolerance (R1 & R2)
TCR
Operating Temperature Range
Power Rating/Resistor
Crosstalk (see Test Circuit)
Package
±1%
±100ppm
0
C to
70
C
100mW
30mV TYP
24 Pin QSOP
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PAC001DTFQR | P/Active 1% Tolerance Dual Thevenin Termination Network |
| PAC003DTFQR | P/Active 1% Tolerance Dual Thevenin Termination Network |
| PAC004DTFQR | P/Active 1% Tolerance Dual Thevenin Termination Network |
| PAC001DTFQT | P/Active 1% Tolerance Dual Thevenin Termination Network |
| PAC002SPFQF | P/Active 1% Tolerance Seriers/Parallel Termination Network |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PACE1750A | 制造商:PYRAMID 制造商全稱:Pyramid Semiconductor Corporation 功能描述:SINGLE CHIP, 15MHz to 40MHz, CMOS 16-BIT PROCESSOR |
| PACE1750AE | 制造商:PYRAMID 制造商全稱:Pyramid Semiconductor Corporation 功能描述:SINGLE CHIP, 20MHz to 40MHz, ENHANCED CMOS 16-BIT PROCESSOR |
| PACE1753 | 制造商:PYRAMID 制造商全稱:Pyramid Semiconductor Corporation 功能描述:SINGLE CHIP, 40MHz CMOS MMU/COMBO |
| PACE1754 | 制造商:PYRAMID 制造商全稱:Pyramid Semiconductor Corporation 功能描述:SINGLE CHIP, 40MHz CMOS PROCESSOR INTERFACE CIRCUIT (PIC) |
| PACE1757M | 制造商:PYRAMID 制造商全稱:Pyramid Semiconductor Corporation 功能描述:COMPLETE EMBEDDED CPU SUBSYSTEM |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。