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參數(shù)資料
| 型號： | P912XDP512J1VFVR |
| 廠商： | 飛思卡爾半導(dǎo)體(中國)有限公司 |
| 英文描述： | Covers, S12XD, S12XB & S12XA Families |
| 中文描述： | 封面，S12XD，S12XB |
| 文件頁數(shù)： | 1051/1350頁 |
| 文件大?。?/td> | 3951K |
| 代理商： | P912XDP512J1VFVR |
Chapter 25 2 Kbyte EEPROM Module (S12XEETX2KV1)
MC9S12XDP512 Data Sheet, Rev. 2.17
Freescale Semiconductor
1051
All EDHI and EDLO bits are readable and writable in special modes.
25.4
Functional Description
25.4.1
EEPROM Command Operations
Write operations are used to execute program, erase, erase verify, sector erase abort, and sector modify
algorithms described in this section. The program, erase, and sector modify algorithms are controlled by
a state machine whose timebase, EECLK, is derived from the oscillator clock via a programmable divider.
The command register as well as the associated address and data registers operate as a buffer and a register
(2-stage FIFO) so that a second command along with the necessary data and address can be stored to the
buffer while the first command is still in progress. Buffer empty as well as command completion are
signalled by flags in the EEPROM status register with interrupts generated, if enabled.
The next sections describe:
1. How to write the ECLKDIV register
2. Command write sequences to program, erase, erase verify, sector erase abort, and sector modify
operations on the EEPROM memory
3. Valid EEPROM commands
4. Effects resulting from illegal EEPROM command write sequences or aborting EEPROM
operations
25.4.1.1
Writing the ECLKDIV Register
Prior to issuing any EEPROM command after a reset, the user is required to write the ECLKDIV register
to divide the oscillator clock down to within the 150 kHz to 200 kHz range. Since the program and erase
timings are also a function of the bus clock, the ECLKDIV determination must take this information into
account.
If we define:
ECLK as the clock of the EEPROM timing control block
Tbus as the period of the bus clock
INT(x) as taking the integer part of x (e.g., INT(4.323)=4)
then ECLKDIV register bits PRDIV8 and EDIV[5:0] are to be set as described in
Figure 25-17
.
For example, if the oscillator clock frequency is 950 kHz and the bus clock frequency is 10 MHz,
ECLKDIV bits EDIV[5:0] should be set to 0x04 (000100) and bit PRDIV8 set to 0. The resulting EECLK
frequency is then 190 kHz. As a result, the EEPROM program and erase algorithm timings are increased
over the optimum target by:
200
190
–
(
)
200
If the oscillator clock frequency is 16 MHz and the bus clock frequency is 40 MHz, ECLKDIV bits
EDIV[5:0] should be set to 0x0A (001010) and bit PRDIV8 set to 1. The resulting EECLK frequency is
100
×
5%
=
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| P912XDP512J1VPVR | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:HCS12X Microcontrollers |
| P912XEQ512J2MAL | 制造商:Freescale Semiconductor 功能描述: |
| P913 | 功能描述:重負荷電源連接器 SB350 CR HOUSING ONLY, RED RoHS:否 制造商:Hirose Connector 系列:PS2 產(chǎn)品類型:Connectors 位置/觸點數(shù)量: 端接類型:Crimp 觸點材料: 觸點電鍍:Gold 電壓額定值: 電流額定值:300 A 附件類型: |
| P9-131121 | 制造商:OTTO 功能描述:Pushbutton Switches Flush Dome QuickConn 5A SPST-DB, SPDT-DB 制造商:OTTO Engineering Inc 功能描述:Switch Push Button N.O. Flush Dome 5A 115VAC 28VDC Momentary Contact Quick Connect Panel Mount |
| P9-131121W | 功能描述:按鈕開關(guān) Flush Dome QuickConn 5A SPST-DB, SPDT-DB RoHS:否 制造商:OTTO 觸點形式: 開關(guān)功能: 電流額定值: 電壓額定值 AC: 電壓額定值 DC: 功率額定值: 安裝風格: 照明: 照明顏色: IP 等級: 端接類型: 觸點電鍍: 執(zhí)行器: 蓋顏色: 封裝: 可燃性等級: |
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