
Chapter 19 Debug (S12XDBGV2)
MC9S12XDP512 Data Sheet, Rev. 2.17
702
Freescale Semiconductor
19.3.1.4
Debug Control Register2 (DBGC2)
Read: Anytime
Write: Anytime the module is disarmed.
This register configures the comparators for range matching.
11
Trace only in range from comparator C to comparator D
Table 19-11. TRCMOD Trace Mode Bit Encoding
TRCMOD
Description
00
01
10
11
NORMAL
LOOP1
DETAIL
Reserved
Table 19-12. TALIGN Trace Alignment Encoding
TALIGN
Description
00
01
10
11
Trigger at end of stored data
Trigger before storing data
Trace buffer entries before and after trigger
Reserved
0x0023
7
0
6
0
5
0
4
0
3
2
1
0
R
W
CDCM
ABCM
Reset
0
0
0
0
0
0
0
0
Unimplemented or Reserved
Figure 19-6. Debug Control Register2 (DBGC2)
Table 19-13. DBGC2 Field Descriptions
Field
Description
3–2
CDCM[3:2]
C and D Comparator Match Control
— These bits determine the C and D comparator match mapping as
described in
Table 19-14
.
1–0
ABCM[1:0]
A and B Comparator Match Control
— These bits determine the A and B comparator match mapping as
described in
Table 19-15
.
Table 19-10. TRANGE Trace Range Encoding
TRANGE
Tracing Source