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| 型號： | P912XDP512F0VAAR |
| 廠商： | 飛思卡爾半導(dǎo)體(中國)有限公司 |
| 英文描述： | Covers, S12XD, S12XB & S12XA Families |
| 中文描述： | 封面，S12XD，S12XB |
| 文件頁數(shù)： | 804/1350頁 |
| 文件大?。?/td> | 3951K |
| 代理商： | P912XDP512F0VAAR |
Chapter 21 External Bus Interface (S12XEBIV2)
MC9S12XDP512 Data Sheet, Rev. 2.17
804
Freescale Semiconductor
21.5.2.1
Example 2a: Emulation Single-Chip Mode
This mode is used for emulation systems in which the target application is operating in normal single-chip
mode.
Figure 21-5
shows the PRU connection with the available external bus signals in an emulator application.
Figure 21-5. Application in Emulation Single-Chip Mode
The timing diagram for this operation is shown in:
Figure ‘Example 2a: Emulation Single-Chip Mode — Read Followed by Write’
The associated timing numbers are given in:
Table ‘Example 2a: Emulation Single-Chip Mode Timing (EWAITE = 0)’
Timing considerations:
SignalsmuxedwithaddresslinesADDRx,i.e.,IVDx,IQSTATxandACCx,havethesametiming.
LSTRB has the same timing as R/W.
ECLKX2 rising edges have the same timing as ECLK edges.
ThetimingforaccessestoPRUregisters,whichtake2cyclestocomplete,isthesameasthetiming
for an external non-PRR access with 1 cycle of stretch as shown in example 2b.
S12X_EBI
ADDR[22:0]/IVD[15:0]
DATA[15:0]
ECLK
ECLKX2
LSTRB
R/W
ADDR[22:20]/ACC[2:0]
ADDR[19:16]/
IQSTAT[3:0]
PRR
Ports
PRU
EMULMEM
Emulator
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| P912XDP512F0VAG | Covers, S12XD, S12XB & S12XA Families |
| P912XDP512F0VAGR | Covers, S12XD, S12XB & S12XA Families |
| P912XDP512F0VAL | Covers, S12XD, S12XB & S12XA Families |
| P912XDP512F0VALR | Covers, S12XD, S12XB & S12XA Families |
| P912XDP512F0VFU | Covers, S12XD, S12XB & S12XA Families |
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