
Appendix G Detailed Register Map
MC9S12XDP512 Data Sheet, Rev. 2.17
Freescale Semiconductor
1311
0x001D
Reserved
R
W
R
W
R
W
0
0
0
0
0
0
0
0
0x001E
IRQCR
IRQE
IRQEN
0
0
0
0
0
0
0x001F
Reserved
0
0
0
0
0
0
0
0
0x0020–0x0027 Debug Module (S12XDBG) Map
Address
Name
Bit 7
Bit 6
0
TRIG
EXTF
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0x0020
DBGC1
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
ARM
XGSBPE
BDM
DBGBRK
COMRV
0x0021
DBGSR
TBF
0
0
0
SSF2
SSF1
SSF0
0x0022
DBGTCR
TSOURCE
TRANGE
TRCMOD
TALIGN
0x0023
DBGC2
0
0
0
0
CDCM
ABCM
0x0024
DBGTBH
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
0x0025
DBGTBL
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0x0026
DBGCNT
0
CNT
0x0027
DBGSCRX
0
0
0
0
SC3
SC2
SC1
SC0
0x0028
1
1
This represents the contents if the Comparator A or C control register is blended into this address
DBGXCTL
(COMPA/C)
DBGXCTL
(COMPB/D)
0
NDB
TAG
BRK
RW
RWE
SRC
COMPE
0x0028
2
SZE
SZ
TAG
BRK
RW
RWE
SRC
COMPE
0x0029
DBGXAH
0
Bit 22
21
20
19
18
17
Bit 16
0x002A
DBGXAM
Bit 15
14
13
12
11
10
9
Bit 8
0x002B
DBGXAL
Bit 7
6
5
4
3
2
1
Bit 0
0x002C
DBGXDH
Bit 15
14
13
12
11
10
9
Bit 8
0x002D
DBGXDL
Bit 7
6
5
4
3
2
1
Bit 0
0x002E
DBGXDHM
Bit 15
14
13
12
11
10
9
Bit 8
0x002F
DBGXDLM
Bit 7
6
5
4
3
2
1
Bit 0
0x001C–0x001F Port Integration Module (PIM) Map 3 of 5
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0