參數(shù)資料
型號： P90CE201
廠商： NXP Semiconductors N.V.
英文描述： 16-bit microcontroller
中文描述： 16位微控制器
文件頁數(shù)： 20/77頁
文件大小： 235K
代理商： P90CE201
August 1993
20
Philips Semiconductors
Product specification
16-bit microcontroller
P90CE201
6.2.4
L
ATCHED
I
NTERRUPT
R
EGISTER
n (LIRn)
Table 6
Description of LIRn bits.
Table 7
Interrupt INTNn control.
Table 8
Selection of interrupt priority level.
SYMBOL
BIT
FUNCTION
INTNC1
INTNC0
AVN
LIRn.7
LIRn.6
LIRn.5
Interrupt Control. These two bits enable/disable the external interrupt INTNn, or
select the pin as an I/O port. See Table 7.
Autovector. When AVN = 0; INTNn is an autovectored interrupt and the processor
calculates the appropriate vector from a fixed vector table. This is also the default
value. When AVN = 1; INTNn is a vectored interrupt and the peripheral must provide
an 8-bit vector number.
Not used; reserved
Pending Interrupt Request. If PIR = 1; then a valid interrupt request has been
detected. It is automatically reset by the interrupt acknowledge cycle from the
CPU. If PIR = 0; there is no pending interrupt request; this is also the default value.
PIR can be set or reset by software by writing a logic 1 or logic 0 respectively to PIRn.
Interrupt Priority Level. These three bits select the interrupt priority level for the
external interrupt INTNn. See Table 8.
LIRn.4
LIRn.3
PIR
IPL2
IPL1
IPL0
LIRn.2
LIRn.1
LIRn.0
INTNC1
INTNC0
INTERRUPT CONTROL
0
0
1
1
0
1
0
1
Interrupt disabled; this is also the default value.
interrupt enabled
Interrupt pin is selected as an I/O port.
Reserved
IPL2
IPL1
IPL0
PRIORITY LEVEL
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Interrupt inhibited; this is also the default value.
Level 1
Level 2
Level 3
Level 4
Level 5
Level 6
Level 7
Fig.12 Latched Interrupt Register n (LIRn).
bit 7
INTNC1
bit 6
INTNC0
bit 5
AVN
bit 4
bit 3
PIR
bit 2
IPL2
bit 1
IPL1
bit 0
IPL0
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