參數(shù)資料
型號: P89V662FBC,557
廠商: NXP Semiconductors
文件頁數(shù): 19/90頁
文件大小: 0K
描述: IC 80C51 MCU FLASH 32K 44-TQFP
產(chǎn)品培訓模塊: Migrating from 8/16-Bit MCUs to 32-Bit ARMs
標準包裝: 800
系列: 89V
核心處理器: 8051
芯體尺寸: 8-位
速度: 40MHz
連通性: I²C,SPI,UART/USART
外圍設備: POR,PWM,WDT
輸入/輸出數(shù): 36
程序存儲器容量: 32KB(32K x 8)
程序存儲器類型: 閃存
RAM 容量: 1K x 8
電壓 - 電源 (Vcc/Vdd): 4.5 V ~ 5.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-TQFP
包裝: 托盤
配用: 622-1001-ND - USB IN-CIRCUIT PROG 80C51ISP
其它名稱: 568-2435
568-2435-ND
568-8271
935280832557
P89V662FBC
P89V660_662_664
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 3.1 — 17 October 2011
26 of 90
NXP Semiconductors
P89V660/662/664
80C51 with 512 B/1 kB/2 kB RAM, dual I2C-bus, SPI
6.4.1 I2C-bus data register
S1DAT register contains the data to be transmitted or the data received. The CPU can
read and write to this 8-bit register while it is not in the process of shifting a byte. Thus this
register should only be accessed when the SI bit is set. Data in S1DAT remains stable as
long as the SI bit is set. Data in S1DAT is always shifted from right to left: the first bit to be
transmitted is the MSB (bit 7), and after a byte has been received, the first bit of received
data is located at the MSB of S1DAT.
6.4.2 I2C-bus slave address register
The S1ADR register is readable and writable, and is only used when the I2C-bus interface
is set to slave mode. In master mode, this register has no effect. The LSB of S1ADR is
general call bit. When this bit is set, the general call address (00H) is recognized.
6.4.3 I2C-bus control register
The CPU can read and write this register. There are two bits are affected by hardware: the
SI bit and the STO bit. The SI bit is set by hardware and the STO bit is cleared by
hardware.
CR2:0 determines the SCL source and frequency when the I2C-bus is in master mode. In
slave mode these bits are ignored and the bus will automatically synchronize with any
clock frequency up to 100 kHz from the master I2C-bus device. Timer 1 should be
programmed by the user in 8 bit auto-reload mode (Mode 2) when used as the SCL
source. See Table 17.
The STA bit is START flag. Setting this bit causes the I2C-bus interface to enter master
mode and attempt transmitting a START condition or transmitting a repeated START
condition when it is already in master mode.
The STO bit is STOP flag. Setting this bit causes the I2C-bus interface to transmit a STOP
condition in master mode, or recovering from an error condition in slave mode.
If the STA and STO are both set, then a STOP condition is transmitted to the I2C-bus if it is
in master mode, and transmits a START condition afterwards. If it is in slave mode, an
internal STOP condition will be generated, but it is not transmitted to the bus.
Table 13.
I2C-bus slave address register (S1ADR - address DBH) bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
S1ADR.6 S1ADR.5 S1ADR.4 S1ADR.3 S1ADR.2 S1ADR.1 S1ADR.0 S1GC
Reset
0000
Table 14.
I2C-bus slave address register (S1ADR - address DBH) bit description
Bit
Symbol
Description
7:1
S1ADR7:1 7 bit own slave address. When in master mode, the contents of this register has
no effect.
0
S1GC
General call bit. When set, the general call address (00H) is recognized,
otherwise it is ignored.
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