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參數(shù)資料
| 型號(hào)： | P89V51RD2FBC,557 |
| 廠商： | NXP Semiconductors |
| 文件頁(yè)數(shù)： | 13/80頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC 80C51 MCU FLASH 64K 44-TQFP |
| 產(chǎn)品培訓(xùn)模塊： | Migrating from 8/16-Bit MCUs to 32-Bit ARMs |
| 標(biāo)準(zhǔn)包裝： | 800 |
| 系列： | 89V |
| 核心處理器： | 8051 |
| 芯體尺寸： | 8-位 |
| 速度： | 40MHz |
| 連通性： | SPI，UART/USART |
| 外圍設(shè)備： | 欠壓檢測(cè)/復(fù)位，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 32 |
| 程序存儲(chǔ)器容量： | 64KB（64K x 8） |
| 程序存儲(chǔ)器類型： | 閃存 |
| RAM 容量： | 1K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 4.5 V ~ 5.5 V |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 44-TQFP |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁(yè)面： | 706 (CN2011-ZH PDF) |
| 配用： | 622-1017-ND - BOARD 44-ZIF PLCC SOCKET 622-1001-ND - USB IN-CIRCUIT PROG 80C51ISP |
| 其它名稱： | 568-1291 935276047557 P89V51RD2FBC |
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P89V51RB2_RC2_RD2_5
NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 12 November 2009
20 of 80
NXP Semiconductors
P89V51RB2/RC2/RD2
8-bit microcontrollers with 80C51 core
6.3 Flash memory IAP
6.3.1 Flash organization
The P89V51RB2/RC2/RD2 program memory consists of a 16/32/64 kB block. ISP
capability, in a second 8 kB block, is provided to allow the user code to be programmed
in-circuit through the serial port. There are three methods of erasing or programming of
the ash memory that may be used. First, the ash may be programmed or erased in the
end-user application by calling low-level routines through a common entry point (IAP).
Second, the on-chip ISP bootloader may be invoked. This ISP bootloader will, in turn, call
low-level routines through the same common entry point that can be used by the end-user
application. Third, the ash may be programmed or erased using the parallel method by
using a commercially available EPROM programmer which supports this device.
6.3.2 Boot block (block 1)
When the microcontroller programs its own ash memory, all of the low level details are
handled by code that is contained in block 1. A user program calls the common entry point
in the block 1 with appropriate parameters to accomplish the desired operation. Boot block
operations include erase user code, program user code, program security bits, etc.
Fig 7.
Dual data pointer organization
Table 10.
AUXR1 - Auxiliary register 1 (address A2H) bit allocation
Not bit addressable; Reset value 00H
Bit
7
6
5
4
3
2
1
0
Symbol
-
GF2
0
-
DPS
Table 11.
AUXR1 - Auxiliary register 1 (address A2H) bit description
Bit
Symbol
Description
7 to 4
-
Reserved for future use. Should be set to ‘0’ by user programs.
3
GF2
General purpose user-dened ag.
2
0
This bit contains a hard-wired ‘0’. Allows toggling of the DPS bit by
incrementing AUXR1, without interfering with other bits in the register.
1
-
Reserved for future use. Should be set to ‘0’ by user programs.
0
DPS
Data pointer select. Chooses one of two Data Pointers for use by the
program. See text for details.
DPL
82H
DPS = 0
→ DPTR0
DPS = 1
→ DPTR1
external data memory
DPS
002aaa518
DPH
83H
DPTR0
DPTR1
AUXR1 / bit0
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| P89V51RD2FN | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:8-bit 80C51 5 V low power 16/32/64 kB flash microcontroller with 1 kB RAM |
| P89V51RD2FN,112 | 功能描述:8位微控制器 -MCU 80C51 64K FL / 1K RM RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| P89V52X2 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:8-bit 80C51 low power 8 kB flash microcontroller with 256 B RAM, 192 B data EEPROM |
| P89V52X2FA | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:8-bit 80C51 low power 8 kB flash microcontroller with 256 B RAM, 192 B data EEPROM |
| P89V52X2FA,512 | 功能描述:8位微控制器 -MCU 80C51 8K FL / 256 RM RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
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