參數(shù)資料
型號(hào): P89V51RB2FA,529
廠商: NXP Semiconductors
文件頁(yè)數(shù): 67/80頁(yè)
文件大?。?/td> 0K
描述: IC 80C51 MCU FLASH 16K 44-PLCC
產(chǎn)品培訓(xùn)模塊: Migrating from 8/16-Bit MCUs to 32-Bit ARMs
標(biāo)準(zhǔn)包裝: 156
系列: 89V
核心處理器: 8051
芯體尺寸: 8-位
速度: 40MHz
連通性: SPI,UART/USART
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 32
程序存儲(chǔ)器容量: 16KB(16K x 8)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 1K x 8
電壓 - 電源 (Vcc/Vdd): 4.5 V ~ 5.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-LCC(J 形引線)
包裝: 管件
產(chǎn)品目錄頁(yè)面: 706 (CN2011-ZH PDF)
配用: 622-1017-ND - BOARD 44-ZIF PLCC SOCKET
622-1001-ND - USB IN-CIRCUIT PROG 80C51ISP
其它名稱: 568-2427-5
935278706529
P89V51RB2FA-S
P89V51RB2_RC2_RD2_5
NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 12 November 2009
7 of 80
NXP Semiconductors
P89V51RB2/RC2/RD2
8-bit microcontrollers with 80C51 core
P1.2/ECI
3
42
4
I/O
P1.2 — Port 1 bit 2.
I
ECI — External clock input. This signal is the external
clock input for the PCA.
P1.3/CEX0
4
43
5
I/O
P1.3 — Port 1 bit 3.
I/O
CEX0 — Capture/compare external I/O for PCA Module 0.
Each capture/compare module connects to a Port 1 pin for
external I/O. When not used by the PCA, this pin can
handle standard I/O.
P1.4/SS/CEX1 5
44
6
I/O
P1.4 — Port 1 bit 4.
I
SS — Slave port select input for SPI.
I/O
CEX1 — Capture/compare external I/O for PCA Module 1.
P1.5/MOSI/
CEX2
6
1
7
I/O
P1.5 — Port 1 bit 5.
I/O
MOSI — Master Output Slave Input for SPI.
I/O
CEX2 — Capture/compare external I/O for PCA Module 2.
P1.6/MISO/
CEX3
7
2
8
I/O
P1.6 — Port 1 bit 6.
I/O
MISO — Master Input Slave Output for SPI.
I/O
CEX3 — Capture/compare external I/O for PCA Module 3.
P1.7/SPICLK/
CEX4
8
3
9
I/O
P1.7 — Port 1 bit 7.
I/O
SPICLK — Serial clock input/output for SPI.
I/O
CEX4 — Capture/compare external I/O for PCA Module 4.
P2.0 to P2.7
I/O with
internal
pull-up
Port 2: Port 2 is an 8-bit bidirectional I/O port with internal
pull-ups. Port 2 pins are pulled HIGH by the internal
pull-ups when ‘1’s are written to them and can be used as
inputs in this state. As inputs, Port 2 pins that are
externally pulled LOW will source current (IIL) because of
the internal pull-ups. Port 2 sends the high-order address
byte during fetches from external program memory and
during accesses to external Data Memory that use 16-bit
address (MOVX@DPTR). In this application, it uses strong
internal pull-ups when transitioning to ‘1’s. Port 2 also
receives some control signals and a partial of high-order
address bits during the external host mode programming
and verication.
P2.0/A8
21
18
24
I/O
P2.0 — Port 2 bit 0.
O
A8 — Address bit 8.
P2.1/A9
22
19
25
I/O
P2.1 — Port 2 bit 1.
O
A9 — Address bit 9.
P2.2/A10
23
20
26
I/O
P2.2 — Port 2 bit 2.
O
A10 — Address bit 10.
P2.3/A11
24
21
27
I/O
P2.3 — Port 2 bit 3.
O
A11 — Address bit 11.
P2.4/A12
25
22
28
I/O
P2.4 — Port 2 bit 4.
O
A12 — Address bit 12.
Table 3.
P89V51RB2/RC2/RD2 pin description …continued
Symbol
Pin
Type
Description
DIP40
TQFP44
PLCC44
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