參數(shù)資料
型號(hào): P89LPC983FDH,529
廠商: NXP Semiconductors
文件頁數(shù): 17/85頁
文件大小: 0K
描述: IC 80C51 MCU 4KB FLASH 28TSSOP
標(biāo)準(zhǔn)包裝: 51
系列: LPC900
核心處理器: 8051
芯體尺寸: 8-位
速度: 18MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 26
程序存儲(chǔ)器容量: 4KB(4K x 8)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 256 x 8
電壓 - 電源 (Vcc/Vdd): 2.4 V ~ 5.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 28-TSSOP(0.173",4.40mm 寬)
包裝: 管件
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P8
9LPC
980_9
82_9
83_9
85
NXP
B.V
.
2010.
Al
lr
ig
h
ts
re
s
e
rv
ed.
Produ
ct
d
a
ta
sheet
Rev
.4
15
J
une
2010
24
o
f85
N
X
P
Semi
conductor
s
P89LPC980/982/983/985
8-
bit
microc
ont
roller
with
a
cce
lerat
e
d
tw
o-
cloc
k
80C5
1
core
DPL
Data pointer low
82H
00
0000 0000
FMADRH
Program flash
address high
E7H
00
0000 0000
FMADRL
Program flash
address low
E6H
00
0000 0000
FMCON
Program flash
control (Read)
E4H
BUSY
-
HVA
HVE
SV
OI
70
0111 0000
Program flash
control (Write)
E4H
FMCMD.7 FMCMD.6 FMCMD.5 FMCMD.4 FMCMD.3 FMCMD.2 FMCMD.1 FMCMD.0
FMDATA
Program flash
data
E5H
00
0000 0000
I2ADR
I2C-bus slave
address register
DBH
I2ADR.6
I2ADR.5
I2ADR.4
I2ADR.3
I2ADR.2
I2ADR.1
I2ADR.0
GC
00
0000 0000
Bit address
DF
DE
DDDCDB
DA
D9
D8
I2CON*
I2C-bus control
register
D8H
-
I2EN
STA
STO
SI
AA
-
CRSEL
00
x000 00x0
I2DAT
I2C-bus data
register
DAH
I2SCLH
Serial clock
generator/SCL
duty cycle
register high
DDH
00
0000 0000
I2SCLL
Serial clock
generator/SCL
duty cycle
register low
DCH
00
0000 0000
I2STAT
I2C-bus status
register
D9H
STA.4
STA.3
STA.2
STA.1
STA.0
0
F8
1111 1000
Bit address
AF
AE
ADACAB
AA
A9
A8
IEN0*
Interrupt enable
0
A8H
EA
EWDRT
EBO
ES/ESR
ET1
EX1
ET0
EX0
00
0000 0000
Bit address
EF
EE
EDEC
EBEA
E9
E8
IEN1*
Interrupt enable
1
E8H
EAD
EST
-
EXTIM
ESPI
EC
EKBI
EI2C
00[2]
00x0 0000
Table 6.
Special function registers - P89LPC983/985 …continued
* indicates SFRs that are bit addressable.
Name
Description
SFR
addr.
Bit functions and addresses
Reset value
MSB
LSB
Hex
Binary
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