參數(shù)資料
型號: P89LPC935FDH,529
廠商: NXP Semiconductors
文件頁數(shù): 29/77頁
文件大?。?/td> 0K
描述: IC 80C51 MCU FLASH 8K 28-TSSOP
產(chǎn)品培訓(xùn)模塊: Migrating from 8/16-Bit MCUs to 32-Bit ARMs
標(biāo)準(zhǔn)包裝: 51
系列: LPC900
核心處理器: 8051
芯體尺寸: 8-位
速度: 12MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,LED,POR,PWM,WDT
輸入/輸出數(shù): 26
程序存儲器容量: 8KB(8K x 8)
程序存儲器類型: 閃存
EEPROM 大小: 512 x 8
RAM 容量: 768 x 8
電壓 - 電源 (Vcc/Vdd): 2.4 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x8b; D/A 2x8b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 28-TSSOP(0.173",4.40mm 寬)
包裝: 管件
產(chǎn)品目錄頁面: 706 (CN2011-ZH PDF)
配用: 622-1014-ND - BOARD FOR LPC9XX TSSOP
622-1008-ND - BOARD FOR LPC9103 10-HVSON
622-1006-ND - SOCKET ADAPTER BOARD
568-4000-ND - DEMO BOARD SPI/I2C TO DUAL UART
568-3510-ND - DEMO BOARD SPI/I2C TO UART
622-1002-ND - USB IN-CIRCUIT PROG LPC9XX
568-1759-ND - EMULATOR DEBUGGER/PROGRMMR LPC9X
568-1758-ND - BOARD EVAL FOR LPC93X MCU FAMILY
其它名稱: 568-1288-5
935274646529
P89LPC935FDH-S
P89LPC933_934_935_936
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 8 — 12 January 2011
35 of 77
NXP Semiconductors
P89LPC933/934/935/936
8-bit microcontroller with accelerated two-clock 80C51 core
not being used as the CPU clock. If the XTAL oscillator is used as the CPU clock, then the
RTC will use CCLK as its clock source. Only power-on reset will reset the RTC and its
associated SFRs to the default state.
8.19 CCU (P89LPC935/936)
This unit features:
A 16-bit timer with 16-bit reload on overflow.
Selectable clock, with prescaler to divide clock source by any integral number
between 1 and 1024.
Four compare/PWM outputs with selectable polarity.
Symmetrical/asymmetrical PWM selection.
Two capture inputs with event counter and digital noise rejection filter.
Seven interrupts with common interrupt vector (one overflow, two capture,
four compare).
Safe 16-bit read/write via shadow registers.
8.19.1 CCU clock
The CCU runs on the CCUCLK, which is either PCLK in basic timer mode, or the output of
a Phase-Locked Loop (PLL). The PLL is designed to use a clock source between 0.5 MHz
to 1 MHz that is multiplied by 32 to produce a CCUCLK between 16 MHz and 32 MHz in
PWM mode (asymmetrical or symmetrical). The PLL contains a 4-bit divider to help divide
PCLK into a frequency between 0.5 MHz and 1 MHz.
8.19.2 CCUCLK prescaling
This CCUCLK can further be divided down by a prescaler. The prescaler is implemented
as a 10-bit free-running counter with programmable reload at overflow.
8.19.3 Basic timer operation
The timer is a free-running up/down counter with a direction control bit. If the timer
counting direction is changed while the counter is running, the count sequence will be
reversed. The timer can be written or read at any time.
When a reload occurs, the CCU Timer Overflow Interrupt Flag will be set, and an interrupt
generated if enabled. The 16-bit CCU timer may also be used as an 8-bit up/down timer.
8.19.4 Output compare
There are four output compare channels A, B, C and D. Each output compare channel
needs to be enabled in order to operate and the user will have to set the associated I/O
pin to the desired output mode to connect the pin. When the contents of the timer matches
that of a capture compare control register, the Timer Output Compare Interrupt Flag
(TOCFx) becomes set. An interrupt will occur if enabled.
8.19.5 Input capture
Input capture is always enabled. Each time a capture event occurs on one of the two input
capture pins, the contents of the timer is transferred to the corresponding 16-bit input
capture register. The capture event can be programmed to be either rising or falling edge
triggered. A simple noise filter can be enabled on the input capture by enabling the Input
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