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參數(shù)資料
| 型號： | P89LPC935FDH,518 |
| 廠商： | NXP Semiconductors |
| 文件頁數(shù)： | 51/77頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC 80C51 MCU 8KB FLASH 28TSSOP |
| 標準包裝： | 2,500 |
| 系列： | LPC900 |
| 核心處理器： | 8051 |
| 芯體尺寸： | 8-位 |
| 速度： | 12MHz |
| 連通性： | I²C，SPI，UART/USART |
| 外圍設備： | 欠壓檢測/復位，LED，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 26 |
| 程序存儲器容量： | 8KB（8K x 8） |
| 程序存儲器類型： | 閃存 |
| EEPROM 大?。?/td> | 512 x 8 |
| RAM 容量： | 768 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.4 V ~ 3.6 V |
| 數(shù)據(jù)轉換器： | A/D 8x8b; D/A 2x8b |
| 振蕩器型： | 內部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 28-TSSOP（0.173"，4.40mm 寬） |
| 包裝： | 帶卷 (TR) |
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P89LPC933_934_935_936
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 8 — 12 January 2011
55 of 77
NXP Semiconductors
P89LPC933/934/935/936
8-bit microcontroller with accelerated two-clock 80C51 core
9.5.3 Edge triggered
An A/D conversion is started by rising or falling edge of P1.4. Once a conversion has
started, additional edge triggers are ignored until the conversion has completed. The edge
triggered start mode is available in all A/D operating modes.
9.5.4 Dual start immediately (P89LPC935/936)
Programming this mode starts a synchronized conversion of both A/D converters. This
start mode is available in all A/D operating modes. Both A/D converters must be in the
same operating mode. In the continuous conversion modes, both A/D converters must
select an identical number of channels. Any trigger of either A/D will start a simultaneous
conversion of both A/Ds.
9.6 Boundary limits interrupt
Each of the A/D converters has both a high and low boundary limit register. After the four
MSBs have been converted, these four bits are compared with the four MSBs of the
boundary high and low registers. If the four MSBs of the conversion are outside the limit
an interrupt will be generated, if enabled. If the conversion result is within the limits, the
boundary limits will again be compared after all 8 bits have been converted. An interrupt
will be generated, if enabled, if the result is outside the boundary limits. The boundary limit
may be disabled by clearing the boundary limit interrupt enable.
9.7 DAC output to a port pin with high output impedance
Each A/D converter’s DAC block can be output to a port pin. In this mode, the ADxDAT3
register is used to hold the value fed to the DAC. After a value has been written to the
DAC (written to ADxDAT3), the DAC output will appear on the channel 3 pin.
9.8 Clock divider
The A/D converter requires that its internal clock source be in the range of 500 kHz to
3.3 MHz to maintain accuracy. A programmable clock divider that divides the clock
from 1 to 8 is provided for this purpose.
9.9 Power-down and Idle mode
In Idle mode the A/C converter, if enabled, will continue to function and can cause the
device to exit Idle mode when the conversion is completed if the A/D interrupt is enabled.
In Power-down mode or Total Power-down mode, the A/D does not function. If the A/D is
enabled, it will consume power. Power can be reduced by disabling the A/D.
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參數(shù)描述 |
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| P89LPC935FDH529 | 制造商:NXP Semiconductors 功能描述:IC 8BIT MCU 80C51 18MHZ TSSOP-28 |
| P89LPC935FHN | 制造商:NXP Semiconductors 功能描述:MCU 8BIT 80C51 8K FLASH HVQFN-28 制造商:NXP Semiconductors 功能描述:MCU 8BIT 80C51 8K FLASH, HVQFN-28 制造商:NXP Semiconductors 功能描述:P89LPC935FHN/HVQFN28/TRAYB// |
| P89LPC935FHN,151 | 功能描述:8位微控制器 -MCU 80C51 8K FL 768B RAM RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
| P89LPC935FHN | 制造商:NXP Semiconductors 功能描述:IC SM MCU 8-BIT 80C51 8K FLASH |
| P89LPC935FHN151 | 制造商:NXP Semiconductors 功能描述:IC 8BIT MCU 80C51 18MHZ 28 |
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