參數(shù)資料
型號: P89LPC932A1FA,129
廠商: NXP Semiconductors
文件頁數(shù): 46/64頁
文件大小: 0K
描述: IC 80C51 MCU FLASH 8K 28-PLCC
產(chǎn)品培訓模塊: Migrating from 8/16-Bit MCUs to 32-Bit ARMs
標準包裝: 37
系列: LPC900
核心處理器: 8051
芯體尺寸: 8-位
速度: 18MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復位,LED,POR,PWM,WDT
輸入/輸出數(shù): 26
程序存儲器容量: 8KB(8K x 8)
程序存儲器類型: 閃存
RAM 容量: 768 x 8
電壓 - 電源 (Vcc/Vdd): 2.4 V ~ 3.6 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 28-PLCC
包裝: 管件
配用: DB-TSSOP-LPC932-ND - BOARD FOR LPC932 TSSOP
622-1014-ND - BOARD FOR LPC9XX TSSOP
622-1008-ND - BOARD FOR LPC9103 10-HVSON
622-1006-ND - SOCKET ADAPTER BOARD
622-1003-ND - KIT FOR LCD DEMO
568-1759-ND - EMULATOR DEBUGGER/PROGRMMR LPC9X
568-1758-ND - BOARD EVAL FOR LPC93X MCU FAMILY
其它名稱: 568-1285-5
935276131129
P89LPC932A1FA-S
P89LPC932A1_3
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 — 12 March 2007
50 of 64
NXP Semiconductors
P89LPC932A1
8-bit microcontroller with accelerated two-clock 80C51 core
Table 10.
Dynamic characteristics (18 MHz)
VDD = 3.0 V to 3.6 V unless otherwise specied.
Tamb = 40 °C to +85 °C for industrial applications, unless otherwise specied.[1][2]
Symbol
Parameter
Conditions
Variable clock
fosc =18MHz Unit
Min
Max
Min
Max
fOSC(RC)
internal RC oscillator frequency
7.189
7.557
7.189
7.557
MHz
fOSC(WD)
internal watchdog oscillator
frequency
280
480
280
480
kHz
fosc
oscillator frequency
0
18
-
MHz
Tcy(CLK)
clock cycle time
55
-
ns
fCLKLP
low power select clock frequency
0
8
-
MHz
Glitch lter
tgr
glitch rejection
P1.5/RST pin
-
50
-
50
ns
any pin except
P1.5/RST
-
15
-
15
ns
tsa
signal acceptance
P1.5/RST pin
125
-
125
-
ns
any pin except
P1.5/RST
50
-
50
-
ns
External clock
tCHCX
clock HIGH time
22
Tcy(CLK) tCLCX
22
-
ns
tCLCX
clock LOW time
22
Tcy(CLK) tCHCX
22
-
ns
tCLCH
clock rise time
-5
-
5
ns
tCHCL
clock fall time
-5
-
5
ns
Shift register (UART mode 0)
tXLXL
serial port clock cycle time
16Tcy(CLK)
-
888
-
ns
tQVXH
output data set-up to clock rising
edge time
13Tcy(CLK)
-
722
-
ns
tXHQX
output data hold after clock rising
edge time
-Tcy(CLK) + 20
-
75
ns
tXHDX
input data hold after clock rising
edge time
-0
-
0
ns
tXHDV
input data valid to clock rising
edge time
150
-
150
-
ns
SPI interface
fSPI
SPI operating frequency
slave
0
CCLK
6
0
3.0
MHz
master
-
CCLK
4
-
4.5
MHz
TSPICYC
SPI cycle time
slave
6
CCLK
-
333
-
ns
master
4
CCLK
-
222
-
ns
tSPILEAD
SPI enable lead time
2.0 MHz (slave)
250
-
250
-
ns
tSPILAG
SPI enable lag time
2.0 MHz (slave)
250
-
250
-
ns
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