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| 型號： | P89LPC931FDH |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 8位微控制器 |
| 英文描述： | 8-bit microcontrollers with two-clock 80C51 core 4 kB-8 kB 3 V Flash with 256-byte data RAM |
| 封裝： | P89LPC930FDH<SOT361-1 (TSSOP28)|<<http://www.nxp.com/packages/SOT361-1.html<1<week 47, 2004,;P89LPC931FDH<SOT361-1 (TSSOP28)|<<http://www.nxp.com/packages/SOT361-1.html&l |
| 文件頁數(shù)： | 31/55頁 |
| 文件大?。?/td> | 267K |
| 代理商： | P89LPC931FDH |
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Philips Semiconductors
P89LPC930/931
8-bit microcontrollers with two-clock 80C51 core
Product data
Rev. 05 — 15 December 2004
37 of 55
9397 750 14472
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
8.22 Watchdog timer
The watchdog timer causes a system reset when it underows as a result of a failure
to feed the timer prior to the timer reaching its terminal count. It consists of a
programmable 12-bit prescaler, and an 8-bit down counter. The down counter is
decremented by a tap taken from the prescaler. The clock source for the prescaler is
either the PCLK or the nominal 400 kHz Watchdog oscillator. The watchdog timer can
only be reset by a power-on reset. When the Watchdog feature is disabled, it can be
used as an interval timer and may generate an interrupt. Figure 14 shows the
watchdog timer in Watchdog mode. Feeding the watchdog requires a two-byte
sequence. If PCLK is selected as the Watchdog clock and the CPU is powered-down,
the watchdog is disabled. The watchdog timer has a time-out period that ranges from
a few
s to a few seconds. Please refer to the P89LPC930/931 User’s Manual for
more details.
8.23 Additional features
8.23.1
Software reset
The SRST bit in AUXR1 gives software the opportunity to reset the processor
completely, as if an external reset or Watchdog reset had occurred. Care should be
taken when writing to AUXR1 to avoid accidental software resets.
8.23.2
Dual data pointers
The dual Data Pointers (DPTR) provides two different Data Pointers to specify the
address used with certain instructions. The DPS bit in the AUXR1 register selects
one of the two Data Pointers. Bit 2 of AUXR1 is permanently wired as a logic ‘0’ so
that the DPS bit may be toggled (thereby switching Data Pointers) simply by
incrementing the AUXR1 register, without the possibility of inadvertently altering other
bits in the register.
(1) Watchdog reset can also be caused by an invalid feed sequence, or by writing to WDCON not immediately followed by a
feed sequence.
Fig 14. Watchdog timer in Watchdog mode (WDTE = ‘1’).
PRE2
PRE1
PRE0
–
WDRUN
WDTOF
WDCLK
WDCON (A7H)
CONTROL REGISTER
PRESCALER
002aaa423
SHADOW
REGISTER
FOR WDCON
8-BIT DOWN
COUNTER
WDL (C1H)
Watchdog
oscillator
PCLK
÷32
MOV WFEED1, #0A5H
MOV WFEED2, #05AH
RESET
see note (1)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| P89LPC931FDH,112 | 功能描述:8位微控制器 -MCU 80C51 8K FL 256B RAM RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| P89LPC931FDH,129 | 功能描述:8位微控制器 -MCU 8K FL/256B RAM/I2C/SPI/TSSOP28 RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| P89LPC931FDH.129 | 制造商:NXP Semiconductors 功能描述:IC 8BIT MCU 8K FLASH SMD 89LC931 |
| P89LPC931FDH.129 | 制造商:NXP Semiconductors 功能描述:IC 8BIT MCU 8K FLASH SMD 89LC931 |
| P89LPC932 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:80C51 8-bit microcontroller with two-clock core 8 KB 3 V low-power Flash with 512-byte data EEPROM |
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