參數(shù)資料
型號(hào): P89LPC930FDH
廠商: NXP Semiconductors N.V.
元件分類(lèi): 8位微控制器
英文描述: 8-bit microcontrollers with two-clock 80C51 core 4 kB-8 kB 3 V Flash with 256-byte data RAM
封裝: P89LPC930FDH<SOT361-1 (TSSOP28)|<<http://www.nxp.com/packages/SOT361-1.html<1<week 47, 2004,;P89LPC931FDH<SOT361-1 (TSSOP28)|<<http://www.nxp.com/packages/SOT361-1.html&l
文件頁(yè)數(shù): 53/55頁(yè)
文件大小: 267K
代理商: P89LPC930FDH
Philips Semiconductors
P89LPC930/931
8-bit microcontrollers with two-clock 80C51 core
Product data
Rev. 05 — 15 December 2004
7 of 55
9397 750 14472
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
P1.0 - P1.7
18, 17, 12,
11, 10, 6,
5, 4
I/O, I [1]
Port 1: Port 1 is an 8-bit I/O port with a user-congurable output type, except for
three pins as noted below. During reset Port 1 latches are congured in the input only
mode with the internal pull-up disabled. The operation of the congurable Port 1 pins
as inputs and outputs depends upon the port conguration selected. Each of the
congurable port pins are programmed independently. Refer to Section 8.11.1 “Port
open drain when used as outputs. P1.5 is input only.
All pins have Schmitt triggered inputs.
Port 1 also provides various special functions as described below:
18
I/O
P1.0 — Port 1 bit 0.
O
TxD — Transmitter output for the serial port.
17
I/O
P1.1 — Port 1 bit 1.
I
RXD — Receiver input for the serial port.
12
I/O
P1.2 — Port 1 bit 2 (open-drain when used as output).
I/O
T0 — Timer/counter 0 external count input or overow output (open-drain when used
as output).
I/O
SCL — I2C serial clock input/output.
11
I
P1.3 — Port 1 bit 3 (open-drain when used as output).
I
INT0 — External interrupt 0 input.
I/O
SDA — I2C serial data input/output.
10
I
P1.4 — Port 1 bit 4.
I
INT1 — External interrupt 1 input.
6I
P1.5 — Port 1 bit 5 (input only).
I
RST — External Reset input during Power-on or if selected via UCFG1. When
functioning as a reset input a LOW on this pin resets the microcontroller, causing I/O
ports and peripherals to take on their default states, and the processor begins
execution at address 0. Also used during a power-on sequence to force In-System
Programming mode. When using an oscillator frequency above 12 MHz, the
reset input function of P1.5 must be enabled. An external circuit is required to
hold the device in reset at power-up until VDD has reached its specied level.
When system power is removed VDD will fall below the minimum specied
operating voltage. When using an oscillator frequency above 12 MHz, in some
applications, an external brownout detect circuit may be required to hold the
device in reset when VDD falls below the minimum specied operating voltage.
5
I/O
P1.6 — Port 1 bit 6.
4
I/O
P1.7 — Port 1 bit 7.
Table 3:
Pin description…continued
Symbol
Pin
Type
Description
相關(guān)PDF資料
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