參數(shù)資料
型號: P89LPC908FD,112
廠商: NXP Semiconductors
文件頁數(shù): 30/51頁
文件大?。?/td> 0K
描述: IC 80C51 MCU FLASH 1K 8-SOIC
產(chǎn)品培訓模塊: Migrating from 8/16-Bit MCUs to 32-Bit ARMs
標準包裝: 1
系列: LPC900
核心處理器: 8051
芯體尺寸: 8-位
速度: 7.3728MHz
連通性: UART/USART
外圍設(shè)備: 欠壓檢測/復位,LED,POR,WDT
輸入/輸出數(shù): 6
程序存儲器容量: 1KB(1K x 8)
程序存儲器類型: 閃存
RAM 容量: 128 x 8
電壓 - 電源 (Vcc/Vdd): 2.4 V ~ 3.6 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
包裝: 剪切帶 (CT)
配用: 622-1015-ND - BOARD FOR LPC908 8-SOIC
622-1008-ND - BOARD FOR LPC9103 10-HVSON
622-1006-ND - SOCKET ADAPTER BOARD
其它名稱: 568-1999-1
Philips Semiconductors
P89LPC906/907/908
8-bit microcontrollers with two-clock 80C51 core
Product data
Rev. 05 — 17 December 2004
36 of 51
9397 750 14467
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
data is received, the 9th data bit goes into RB8 in Special Function Register SCON,
while the stop bit is not saved. The baud rate is programmable to either 1
16 or 132 of
the CPU clock frequency, as determined by the SMOD1 bit in PCON.
8.17.4
Mode 3
11 bits are transmitted (through TxD) or received (through RxD): a start bit
(logical ‘0’), 8 data bits (LSB rst), a programmable 9th data bit, and a stop bit
(logical ‘1’). In fact, Mode 3 is the same as Mode 2 in all respects except baud rate.
The baud rate in Mode 3 is variable and is determined by the Timer 1 overow rate or
the Baud Rate Generator (described in section Section 8.17.5 “Baud rate generator
8.17.5
Baud rate generator and selection
Both devices have an independent Baud Rate Generator. The baud rate is
determined by a baud-rate preprogrammed into the BRGR1 and BRGR0 SFRs which
together form a 16-bit baud rate divisor value that works in a similar manner as
Timer 1. If the baud rate generator is used, Timer 1 can be used for other timing
functions.
The UART can use either Timer 1 or the baud rate generator output (see Figure 15).
Note that Timer T1 is further divided by 2 if the SMOD1 bit (PCON.7) is cleared. The
independent Baud Rate Generator uses CCLK.
8.17.6
Framing error
Framing error is reported in the status register (SSTAT). In addition, if SMOD0
(PCON.6) is ‘1’, framing errors can be made available in SCON.7, respectively. If
SMOD0 is ‘0’, SCON.7 is SM0. It is recommended that SM0 and SM1 (SCON.7:6)
are set up when SMOD0 is ‘0’.
8.17.7
Break detect
Break detect is reported in the status register (SSTAT). A break is detected when
11 consecutive bits are sensed LOW. The break detect can be used to reset the
device.
8.17.8
Double buffering
The UART has a transmit double buffer that allows buffering of the next character to
be written to SBUF while the rst character is being transmitted. Double buffering
allows transmission of a string of characters with only one stop bit between any two
characters, as long as the next character is written between the start bit and the stop
bit of the previous character.
Fig 15. Baud rate sources for UART (Modes 1, 3).
Baud Rate Modes 1 and 3
SBRGS = 1
SBRGS = 0
SMOD1 = 0
SMOD1 = 1
2
Timer 1 Overflow
(PCLK-based)
Baud Rate Generator
(CCLK-based)
002aaa419
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