- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄367742 > P89C664HBBD (NXP SEMICONDUCTORS) 80C51 8-bit Flash microcontroller family PDF資料下載
參數(shù)資料
| 型號： | P89C664HBBD |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 80C51 8-bit Flash microcontroller family |
| 中文描述： | 8-BIT, FLASH, 33 MHz, MICROCONTROLLER, PQFP44 |
| 封裝： | 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-389-1, LQFP-44 |
| 文件頁數(shù)： | 12/89頁 |
| 文件大小： | 491K |
| 代理商： | P89C664HBBD |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁當前第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁
Philips Semiconductors
Product data
P89C660/P89C662/P89C664/
P89C668
80C51 8-bit Flash microcontroller family
16KB/32KB/64KB ISP/IAP Flash with 512B/1KB/2KB/8KB RAM
2002 Oct 28
12
I
2
C SERIAL COMMUNICATION — SIO1
The I
2
C serial port is identical to the I
2
C serial port on the 8XC554,
8XC654, and 8XC652 devices.
Note that the P89C660/662/664/668 I
2
C pins are alternate
functions to port pins P1.6 and P1.7. Because of this, P1.6 and
P1.7 on these parts do not have a pull-up structure as found on the
80C51. Therefore P1.6 and P1.7 have open drain outputs on the
P89C660/662/664/668.
The I
2
C bus uses two wires (SDA and SCL) to transfer information
between devices connected to the bus. The main features of the bus
are:
– Bidirectional data transfer between masters and slaves
– Multimaster bus (no central master)
– Arbitration between simultaneously transmitting masters without
corruption of serial data on the bus
– Serial clock synchronization allows devices with different bit rates
to communicate via one serial bus
– Serial clock synchronization can be used as a handshake
mechanism to suspend and resume serial transfer
– The I
2
C bus may be used for test and diagnostic purposes
The output latches of P1.6 and P1.7 must be set to logic 1 in order
to enable SIO1.
The P89C66x on-chip I
2
C logic provides a serial interface that
meets the I
2
C bus specification and supports all transfer modes
(other than the low-speed mode) from and to the I
2
C bus. The SIO1
logic handles bytes transfer autonomously. It also keeps track of
serial transfers, and a status register (S1STA) reflects the status of
SIO1 and the I
2
C bus.
The CPU interfaces to the I
2
C logic via the following four special
function registers: S1CON (SIO1 control register), S1STA (SIO1
status register), S1DAT (SIO1 data register), and S1ADR (SIO1
slave address register). The SIO1 logic interfaces to the external I
2
C
bus via two port 1 pins: P1.6/SCL (serial clock line) and P1.7/SDA
(serial data line).
A typical I
2
C bus configuration is shown in Figure 1. Figure 2 shows
how a data transfer is accomplished on the bus. Depending on the
state of the direction bit (R/W), two types of data transfers are
possible on the I
2
C bus:
1. Data transfer from a master transmitter to a slave receiver. The
first byte transmitted by the master is the slave address. Next
follows a number of data bytes. The slave returns an
acknowledge bit after each received byte.
2. Data transfer from a slave transmitter to a master receiver. The
first byte (the slave address) is transmitted by the master. The
slave then returns an acknowledge bit. Next follows the data
bytes transmitted by the slave to the master. The master returns
an acknowledge bit after all received bytes other than the last
byte. At the end of the last received byte, a “not acknowledge” is
returned.
The master device generates all of the serial clock pulses and the
START and STOP conditions. A transfer is ended with a STOP
condition or with a repeated START condition. Since a repeated
START condition is also the beginning of the next serial transfer, the
I
2
C bus will not be released.
Modes of Operation
The on-chip SIO1 logic may operate in the following four modes:
1. Master Transmitter mode:
Serial data output through P1.7/SDA while P1.6/SCL outputs the
serial clock. The first transmitted byte contains the slave address
of the receiving device (7 bits) and the data direction bit. In this
mode the data direction bit (R/W) will be logic 0, and we say that
a “W” is transmitted. Thus the first byte transmitted is SLA+W.
Serial data is transmitted 8 bits at a time. After each byte is
transmitted, an acknowledge bit is received. START and STOP
conditions are output to indicate the beginning and the end of a
serial transfer.
2. Master Receiver Mode:
The first transmitted byte contains the slave address of the
transmitting device (7 bits) and the data direction bit. In this
mode the data direction bit (R/W) will be logic 1, and we say that
an “R” is transmitted. Thus the first byte transmitted is SLA+R.
Serial data is received via P1.7/SDA while P1.6/SCL outputs the
serial clock. Serial data is received 8 bits at a time. After each
byte is received, an acknowledge bit is transmitted. START and
STOP conditions are output to indicate the beginning and end of
a serial transfer.
3. Slave Receiver mode:
Serial data and the serial clock are received through P1.7/SDA
and P1.6/SCL. After each byte is received, an acknowledge bit is
transmitted. START and STOP conditions are recognized as the
beginning and end of a serial transfer. Address recognition is
performed by hardware after reception of the slave address and
direction bit.
4. Slave Transmitter mode:
The first byte is received and handled as in the Slave Receiver
mode. However, in this mode, the direction bit will indicate that
the transfer direction is reversed. Serial data is transmitted via
P1.7/SDA while the serial clock is input through P1.6/SCL.
START and STOP conditions are recognized as the beginning
and end of a serial transfer.
In a given application, SIO1 may operate as a master and as a
slave. In the Slave mode, the SIO1 hardware looks for its own slave
address and the general call address. If one of these addresses is
detected, an interrupt is requested. When the microcontroller wishes
to become the bus master, the hardware waits until the bus is free
before the Master mode is entered so that a possible slave action is
not interrupted. If bus arbitration is lost in the Master mode, SIO1
switches to the Slave mode immediately and can detect its own
slave address in the same serial transfer.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| P89C662 | 80C51 8-Bit Flash Microcontroller 32KB ISP/IAP FLASH with 1KB RAM(80C51 8位閃速微控制器，帶16KB ISP/IAP閃速存儲器和1KB RAM) |
| P89C668HBA | 80C51 8-bit Flash microcontroller family 64KB ISP FLASH with 8KB RAM |
| P89C668HFA | 80C51 8-bit Flash microcontroller family 64KB ISP FLASH with 8KB RAM |
| P89C668 | 80C51 8-bit Flash microcontroller family 64KB ISP FLASH with 8KB RAM |
| P89C668HBBD | 80C51 8-bit Flash microcontroller family 64KB ISP FLASH with 8KB RAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| P89C664HBBD/00,557 | 功能描述:8位微控制器 -MCU 64K/2K FL 6 CLK ISP/IAP COM RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
| P89C664HFA | 制造商:PHIL 功能描述: |
| P89C664HFA/00,512 | 功能描述:8位微控制器 -MCU 64K/2K FL 6 CLK ISP/IAP IND RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
| P89C664HFBD | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:80C51 8-bit Flash microcontroller family |
| P89C664HFBD/00,557 | 功能描述:8位微控制器 -MCU 64K/2K FL 6CLK ISP/IAP QFP IND RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
發(fā)布緊急采購，3分鐘左右您將得到回復。