參數(shù)資料
型號(hào): P87LPC768FN,112
廠商: NXP Semiconductors
文件頁(yè)數(shù): 53/65頁(yè)
文件大?。?/td> 0K
描述: IC 80C51 MCU 4K OTP 20-DIP
產(chǎn)品培訓(xùn)模塊: Migrating from 8/16-Bit MCUs to 32-Bit ARMs
標(biāo)準(zhǔn)包裝: 18
系列: LPC700
核心處理器: 8051
芯體尺寸: 8-位
速度: 20MHz
連通性: I²C,UART/USART
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,LED,POR,PWM,WDT
輸入/輸出數(shù): 18
程序存儲(chǔ)器容量: 4KB(4K x 8)
程序存儲(chǔ)器類型: OTP
RAM 容量: 128 x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 4x8b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 20-DIP(0.300",7.62mm)
包裝: 管件
產(chǎn)品目錄頁(yè)面: 706 (CN2011-ZH PDF)
其它名稱: 568-3220-5
935267488112
P87LPC768FN
Philips Semiconductors
Preliminary data
P87LPC768
Low power, low price, low pin count (20 pin) microcontroller
with 4 kB OTP 8-bit A/D, Pulse Width Modulator
2002 Mar 12
55
SYMBOL
PARAMETER
TEST CONDITIONS
LIMITS
UNIT
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIO
Offset voltage comparator inputs1
±10
mV
VCR
Common mode range comparator inputs
0
VDD–0.3
V
CMRR
Common mode rejection ratio1
–50
dB
Response time
250
500
ns
Comparator enable to output valid
10
s
IIL
Input leakage current, comparator
0 < VIN < VDD
±10
A
NOTE:
1. This parameter is guaranteed by characterization, but not tested in production.
A/D CONVERTER DC ELECTRICAL CHARACTERISTICS
Vdd = 3.0V to 6.0V unless otherwise specified;
Tamb = 0 to +70
°C for commercial, -40°C to +85°C for industrial, unless otherwise specified.
SYMBOL
PARAMETER
TEST CONDITIONS
LIMITS
UNIT
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
AVIN
Analog input voltage
VSS - 0.2
VDD + 0.2
V
RREF
Resistance between VDD and VSS
A/D enabled
tbd
k
CIA
Analog input capacitance
15
pF
DLe
Differential non-linearity1,2,3
±1
LSB
ILe
Integral non-linearity1,4
±1
LSB
OSe
Offset error1,5
±2
LSB
Ge
Gain error1,6
±1
%
Ae
Absolute voltage error1,7
±1
LSB
MCTC
Channel-to-channel matching
±1
LSB
Ct
Crosstalk between inputs of port8
0 - 100kHz
-60
dB
-
Input slew rate
100
V/ms
-
Input source impedance
10
k
NOTES:
1. Conditions: VSS = 0V; VDD = 5.12V.
2. The A/D is monotonic, there are no missing codes
3. The differential non-linearity (DLe) is the difference between the actual step width and the ideal step width. See Figure 41.
4. The integral non-linearity (ILe) is the peak difference between the center of the steps of the actual and the ideal transfer curve after
appropriate adjustment of gain and offset errors. See Figure 41.
5. The offset error (OSe) is the absolute difference between the straight line which fits the actual transfer curve (after removing gain error), and
the straight line which fits the ideal transfer curve. See Figure 41.
6. The gain error (Ge) is the relative difference in percent between the straight line fitting the actual transfer curve (after removing offset error),
and the straight line which fits the ideal transfer curve. Gain error is constant at every point on the transfer curve. See Figure 41.
7. The absolute voltage error (Ae) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated
ADC and the ideal transfer curve.
8. This should be considered when both analog and digital signals are input simultaneously to A/D pins.
9. Changing the input voltage faster than this may cause erroneous readings.
10. A source impedance higher than this driving an A/D input may result in loss of precision and erroneous readings.
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