參數(shù)資料
型號： P87CL52X2BDH
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 80C51 8-bit microcontroller family
中文描述： 8-BIT, OTPROM, 33 MHz, MICROCONTROLLER, PDSO38
封裝： 4.40 MM, 0.50 MM PITCH, PLASTIC, SHRINK, SOT-510-1, TSSOP-38
文件頁數(shù)： 35/47頁
文件大?。?/td> 301K
代理商： P87CL52X2BDH
Philips Semiconductors
Product data
P87CL52X2/54X2
80C51 8-bit microcontroller family
8K/16K OTP 256 bytes RAM ROMless low voltage
(1.8 V to 3.3 V), low power, high speed (33 MHz)
2003 May 14
35
AC ELECTRICAL CHARACTERISTICS
T
amb
= 0
°
C to +70
°
C, V
CC
= +1.8 V to +3.3 V, V
SS
= 0 V
1, 2, 3
12 MHz CLOCK
MIN
VARIABLE CLOCK
MIN
1.0
2t
CLCL
–40
t
CLCL
–40
t
CLCL
–30
SYMBOL
1/t
CLCL
t
LHLL
t
AVLL
t
LLAX
t
LLIV
t
LLPL
t
PLPH
t
PLIV
t
PXIX
t
PXIZ
t
AVIV
t
PLAZ
Data Memory
t
RLRH
t
WLWH
t
RLDV
t
RHDX
t
RHDZ
t
LLDV
t
AVDV
t
LLWL
t
AVWL
t
QVWX
t
WHQX
t
QVWH
t
RLAZ
t
WHLH
External Clock
t
CHCX
t
CLCX
t
CLCH
t
CHCL
Shift Register
t
XLXL
t
QVXH
t
XHQX
t
XHDX
t
XHDV
NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified.
2. Load capacitance for port 0, ALE, and PSEN = 100 pF, load capacitance for all other outputs = 80 pF.
3. Interfacing the P87CL5xX2 to devices with float times up to 45 ns is permitted. This limited bus contention will not cause damage to Port 0
drivers.
4. Parts are guaranteed to operate down to 0 Hz. When an external clock source is used, the RST pin should be held high for a minimum of
20
μ
s for power-on or wakeup from power down.
FIGURE
14
20
20
20
20
20
20
20
20
20
20
20
PARAMETER
MAX
MAX
12
UNIT
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Oscillator frequency
4
ALE pulse width
Address valid to ALE low
Address hold after ALE low
ALE low to valid instruction in
ALE low to PSEN low
PSEN pulse width
PSEN low to valid instruction in
Input instruction hold after PSEN
Input instruction float after PSEN
Address to valid instruction in
PSEN low to address float
85
22
32
150
4t
CLCL
–100
32
142
t
CLCL
–30
3t
CLCL
–45
82
3t
CLCL
–105
0
0
37
207
10
t
CLCL
–25
5t
CLCL
–105
10
21, 22
21, 22
21, 22
21, 22
21, 22
21, 22
21, 22
21, 22
21, 22
21, 22
21, 22
22
21, 22
21, 22
RD pulse width
WR pulse width
RD low to valid data in
Data hold after RD
Data float after RD
ALE low to valid data in
Address to valid data in
ALE low to RD or WR low
Address valid to WR low or RD low
Data valid to WR transition
Data hold after WR
Data valid to WR high
RD low to address float
RD or WR high to ALE high
275
275
6t
CLCL
–100
6t
CLCL
–100
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
147
5t
CLCL
–165
0
0
65
350
397
239
2t
CLCL
–60
8t
CLCL
–150
9t
CLCL
–165
3t
CLCL
+50
137
122
13
13
287
3t
CLCL
–50
4t
CLCL
–130
t
CLCL
–50
t
CLCL
–50
7t
CLCL
–150
0
0
23
103
t
CLCL
–40
t
CLCL
+40
24
24
24
24
High time
Low time
Rise time
Fall time
20
20
20
20
t
CLCL
–t
CLCX
t
CLCL
–t
CHCX
20
20
ns
ns
ns
ns
20
20
23
23
23
23
23
Serial port clock cycle time
Output data setup to clock rising edge
Output data hold after clock rising edge
Input data hold after clock rising edge
Clock rising edge to input data valid
750
492
8
0
12t
CLCL
10t
CLCL
–133
2t
CLCL
–117
0
ns
ns
ns
ns
ns
668
10t
CLCL
–165
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