參數(shù)資料
型號(hào)： P87CE560EFB
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： BATTERY CHG UNIV 12VDC @ 500MA
中文描述： 8-BIT, OTPROM, 16 MHz, MICROCONTROLLER, PQFP80
封裝： 14 X 20 X 2.70 MM, PLASTIC, SOT-318-1, QFP-80
文件頁數(shù)： 19/84頁
文件大?。?/td> 441K
代理商： P87CE560EFB
1997 Aug 01
19
Philips Semiconductors
Product specification
8-bit microcontroller
P8xCE560
11 ANALOG-TO-DIGITAL CONVERTER (ADC)
11.1
ADC features
10-bit resolution
8 multiplexed analog inputs
Programmable autoscan of the analog inputs
Bit oriented 8-bit scan-select register to select analog
inputs
Continuous scan or one time scan configurable from
1 to 8 analog inputs
Start of a conversion by software or with an external
signal
Eight 10-bit buffer registers, one register for each analog
input channel
Interrupt request after one channel scan loop
Programmable prescaler (dividing by 2, 4, 6, 8) to adapt
to different system clock frequencies
Conversion time for one analog-to-digital conversion:
15 to 50
μ
s
Differential non-linearity (DL
e
): ±
1 LSB
Integral non-linearity (IL
e
):
±
2 LSB
Offset error (OS
e
): ±
2 LSB
Gain error (G
e
):
±
4%
Absolute voltage error (A
e
): 3 LSB
Channel-to-channel matching (M
ctc
):
±
1 LSB
Crosstalk between analog inputs (C
t
): < 60 dB at
100 kHz
Monotonic and no missing codes
Separated analog (V
DDA
, V
SSA
) and digital (V
DD
, V
SS
)
supply voltages
Reference voltage at two special pins: V
ref(n)(A)
and
V
ref(p)(A)
.
For information on the ADC characteristics, refer to
Chapter 21.
11.2
ADC functional description
The P8xCE560 has a 10-bit successive approximation
ADC with 8 multiplexed analog input channels, comprising
a high input impedance comparator, DAC (built with
1024 series resistors and analog switches), registers and
control logic. Input voltage range is from V
ref(n)(A)
(typical 0 V) to V
ref(p)(A)
(typical +5 V).
Each of the set of 8 buffer registers (10-bit wide) store the
conversion results of the proper analog input channel.
Eleven Special Function Registers (SFRs) perform the
user software interface to the ADC; see Table 14 for an
overview of the ADC SFRs. In order to have a minimum of
ADC service overhead in the microcontroller program, the
ADC is able to operate autonomously within its user
configurable autoscan function.
Figure 10 shows the functional diagram of the ADC.
11.3
ADC timing
A programmable prescaler is controlled by the user
selectable bits ADPR1 and ADPR0 in SFR ADCON to
adapt the conversion time for different microcontroller
clock frequencies.
Table 13 shows conversion times (t
ADC
) for one
analog-to-digital conversion at some convenient system
clock frequencies (f
clk
) and ADC programmable prescaler
divisors:
m
.
Conversion time t
ADC
= (6
×
m + 1) machine cycles.
A conversion time t
ADC
consists of one sample time period
(which equals two bit conversion times), 10 bit conversion
time periods and one machine cycle to store the result.
After result storage an extra initializing time period follows
to select the next analog input channel (according to the
contents of SFR ADPSS), before the input signal is
sampled.Thus the time period between two adjacent
conversions within an autoscan loop is larger than the pure
time t
ADC
. This autoscan cycle time is (7
×
m) machine
cycles.
At the start of an autoscan conversion the time between
writing to SFR ADCON and the first analog input signal
sampling depends on the current prescaler value (
m
) and
the relative time offset between this write operation and the
internal (divided) ADC clock. This gives a variation range
for the analog-to-digital conversion start time of (
1
2
×
m)
machine cycles.
Table 13
Conversion time configuration examples
Note
1.
Prohibited t
ADC
values; for t
ADC
outside the limits of
15
μ
s
≤
t
ADC
≤
50
μ
s, the specified ADC
characteristics are not guaranteed.
m
t
ADC
(
μ
s) at f
CLK
:
6 MHz
8 MHz
12 MHz
13.00
(1)
25.00
37.00
49.00
16 MHz
9.75
(1)
18.75
27.75
36.75
2
4
6
8
26.00
50.00
74.00
(1)
98.00
(1)
19.50
37.50
55.50
(1)
73.50
(1)
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