參數(shù)資料
型號(hào)： P87C592EFA
廠(chǎng)商： NXP SEMICONDUCTORS
元件分類(lèi)： 微控制器/微處理器
英文描述： 8-bit microcontroller with on-chip CAN
中文描述： 8-BIT, OTPROM, 16 MHz, MICROCONTROLLER, PQCC68
文件頁(yè)數(shù)： 15/108頁(yè)
文件大?。?/td> 650K
代理商： P87C592EFA
1996 Jun 27
15
Philips Semiconductors
Product specification
8-bit microcontroller with on-chip CAN
P8xC592
8
I/O PORT STRUCTURE
The P8xC592 has six 8-bit parallel ports: Port 0 to Port 5. In addition to the standard 8-bit parallel ports, the I/O facilities
also include a number of special I/O lines. The use of a Port 1, Port 3 or Port 4 pins as an alternative function is carried
out automatically provided the associated SFR bit is set HIGH.
Table 5
Default
Port functions
Table 6
Alternative
Port functions
PORT
TYPE
FUNCTION
REMARKS
Port 0
Port 1
Port 2
Port 3
Port 4
Port 5
I/O
I/O
I/O
I/O
I/O
I
The same as in the 80C51
Except for the additional functions of P1.6 and
P1.7.
Parallel l/O port
Parallel input port with an input function only
Parallel I/O function is identical to Port1, 2 and 3.
May be used as normal inputs if the ADC function
is inoperative.
PORT
TYPE
FUNCTION
REMARKS
Port 0
I/O
Multiplexed Low-order address and
Data bus for external memory (AD7 to AD0)
Provides the multiplexed Low-order address and
data bus used for expanding the P8xC592 with
standard memories and peripherals.
External interrupt request inputs, if capture
information is not utilized.
Port 1
I/O
Capture timer inputs for Timer T2
(CT0I to CT3I), or
External interrupt request inputs
(INT2 to INT5)
T2 event input (T2)
T2 timer reset input (RT2)
CAN transmitter output 0 (CTX0)
CAN transmitter output 1 (CTX1)
High-order address byte for external memory
(A08 to A15)
External counter input.
External counter reset input.
CTX0 and CTX1 outputs of the CAN interface
(note 1).
Port 2
I/O
Port 2 provides the High-order address bus when
the P8xC592 is expanded with external Program
Memory and/or external Data Memory.
Receiver input of serial port SIO0 (UART).
Transmitter output of serial port SIO0 (UART).
External interrupt request inputs.
Port 3
I/O
Serial Input Port (RXD)
Serial Output Port (TXD)
External interrupt (INT0)
External interrupt (INT1)
Timer 0 external input (T0)
Timer 1 external input (T1)
External data memory Write strobe (WR)
External data memory Read strobe (RD)
Compare and Set/Reset outputs
(CMSR0 to CMSR5)
Compare and toggle outputs (CMT0, CMT1)
Input channels to ADC (ADC7 to ADC0)
Counter inputs.
Control signal to write to external Data Memory.
Control signal to read from external Data Memory.
Can be configured to provide signals indicating a
match between Timer counter T2 and its compare
registers.
Port 4
I/O
Port 5
I
Port 5 may be used in conjunction with the ADC
interface (note 2).
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