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參數(shù)資料
| 型號： | P87C51X2FA,512 |
| 廠商： | NXP Semiconductors |
| 文件頁數(shù)： | 17/62頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC 80C51 MCU 128 RAM 44PLCC |
| 標準包裝： | 26 |
| 系列： | 87C |
| 核心處理器： | 8051 |
| 芯體尺寸： | 8-位 |
| 速度： | 33MHz |
| 連通性： | EBI/EMI，UART/USART |
| 外圍設(shè)備： | POR |
| 輸入/輸出數(shù)： | 32 |
| 程序存儲器容量： | 4KB（4K x 8） |
| 程序存儲器類型： | OTP |
| RAM 容量： | 128 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 5.5 V |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 44-LCC（J 形引線） |
| 包裝： | 管件 |
| 其它名稱： | 568-7911-5 568-7911-5-ND 568-8360-5 935269605512 P87C51X2FA P87C51X2FA,512-ND P87C51X2FA-ND |
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Philips Semiconductors
Product data
P80C3xX2; P80C5xX2;
P87C5xX2
80C51 8-bit microcontroller family
4K/8K/16K/32K ROM/OTP, low voltage (2.7 to 5.5 V),
low power, high speed (30/33 MHz)
2003 Jan 24
24
SM2
Enables the multiprocessor communication feature in Modes 2 and 3. In Mode 2 or 3, if SM2 is set to 1, then Rl will not be
activated if the received 9th data bit (RB8) is 0. In Mode 1, if SM2=1 then RI will not be activated if a valid stop bit was not
received. In Mode 0, SM2 should be 0.
REN
Enables serial reception. Set by software to enable reception. Clear by software to disable reception.
TB8
The 9th data bit that will be transmitted in Modes 2 and 3. Set or clear by software as desired.
RB8
In Modes 2 and 3, is the 9th data bit that was received. In Mode 1, it SM2=0, RB8 is the stop bit that was received. In Mode 0,
RB8 is not used.
TI
Transmit interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or at the beginning of the stop bit in the other
modes, in any serial transmission. Must be cleared by software.
RI
Receive interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or halfway through the stop bit time in the other
modes, in any serial reception (except see SM2). Must be cleared by software.
SM0
SM1
SM2
REN
TB8
RB8
TI
RI
Where SM0, SM1 specify the serial port mode, as follows:
SM0
SM1
Mode
Description
Baud Rate
0
shift register
fOSC/12 (12-clock mode) or fOSC/6 (6-clock mode)
0
1
8-bit UART
variable
1
0
2
9-bit UART
fOSC/64 or fOSC/32 (12-clock mode) or fOSC/32 or fOSC/16 (6-clock mode)
1
3
9-bit UART
variable
SU01626
Bit Addressable
SCON
Address = 98H
Reset Value = 00H
76543
2
1
0
Figure 12. Serial Port Control (SCON) Register
Baud Rate
f
SMOD
Timer 1
Mode
12-clock mode
6-clock mode
fOSC
SMOD
C/T
Mode
Reload Value
Mode 0 Max
1.67 MHz
3.34 MHz
20 MHz
X
Mode 2 Max
625 k
1250 k
20 MHz
1
X
Mode 1, 3 Max
104.2 k
208.4 k
20 MHz
1
0
2
FFH
Mode 1, 3
19.2 k
38.4 k
11.059 MHz
1
0
2
FDH
9.6 k
19.2 k
11.059 MHz
0
2
FDH
4.8 k
9.6 k
11.059 MHz
0
2
FAH
2.4 k
4.8 k
11.059 MHz
0
2
F4H
1.2 k
2.4 k
11.059 MHz
0
2
E8H
137.5
275
11.986 MHz
0
2
1DH
110
220
6 MHz
0
2
72H
110
220
12 MHz
0
1
FEEBH
Figure 13. Timer 1 Generated Commonly Used Baud Rates
More About Mode 0
Serial data enters and exits through RxD. TxD outputs the shift
clock. 8 bits are transmitted/received: 8 data bits (LSB first). The
baud rate is fixed a 1/12 the oscillator frequency (12-clock mode) or
1/6 the oscillator frequency (6-clock mode).
Figure 14 shows a simplified functional diagram of the serial port in
Mode 0, and associated timing.
Transmission is initiated by any instruction that uses SBUF as a
destination register. The “write to SBUF” signal at S6P2 also loads a
1 into the 9th position of the transmit shift register and tells the TX
Control block to commence a transmission. The internal timing is
such that one full machine cycle will elapse between “write to SBUF”
and activation of SEND.
SEND enables the output of the shift register to the alternate output
function line of P3.0 and also enable SHIFT CLOCK to the alternate
output function line of P3.1. SHIFT CLOCK is low during S3, S4, and
S5 of every machine cycle, and high during S6, S1, and S2. At
S6P2 of every machine cycle in which SEND is active, the contents
of the transmit shift are shifted to the right one position.
As data bits shift out to the right, zeros come in from the left. When
the MSB of the data byte is at the output position of the shift register,
then the 1 that was initially loaded into the 9th position, is just to the
left of the MSB, and all positions to the left of that contain zeros.
This condition flags the TX Control block to do one last shift and
then deactivate SEND and set T1. Both of these actions occur at
S1P1 of the 10th machine cycle after “write to SBUF.”
Reception is initiated by the condition REN = 1 and R1 = 0. At S6P2
of the next machine cycle, the RX Control unit writes the bits
11111110 to the receive shift register, and in the next clock phase
activates RECEIVE.
RECEIVE enable SHIFT CLOCK to the alternate output function line
of P3.1. SHIFT CLOCK makes transitions at S3P1 and S6P1 of
every machine cycle. At S6P2 of every machine cycle in which
RECEIVE is active, the contents of the receive shift register are
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