80C51 8-bit microcontroller family 8KB/16KB/32KB/64K" />
參數(shù)資料
型號： P87C51RC2FN,112
廠商： NXP Semiconductors
文件頁數(shù)： 37/67頁
文件大?。?/td> 0K
描述： IC 80C51 MCU 512 RAM 40DIP
產品培訓模塊： Migrating from 8/16-Bit MCUs to 32-Bit ARMs
標準包裝： 9
系列： 87C
核心處理器： 8051
芯體尺寸： 8-位
速度： 33MHz
連通性： EBI/EMI，UART/USART
外圍設備： POR，PWM，WDT
輸入/輸出數(shù)： 32
程序存儲器容量： 32KB（32K x 8）
程序存儲器類型： OTP
RAM 容量： 512 x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 5.5 V
振蕩器型： 內部
工作溫度： -40°C ~ 85°C
封裝/外殼： 40-DIP（0.600"，15.24mm）
包裝： 管件
其它名稱： 568-7906-5
568-7906-5-ND
568-8356-5
935272151112
P87C51RC2FN
P87C51RC2FN,112-ND
P87C51RC2FN-ND
Philips Semiconductors
Product data
P87C51RA2/RB2/RC2/RD2
80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP
with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high
speed (30/33 MHz)
2003 Jan 24
42
ERAM
256 or 768 BYTES
UPPER
128 BYTES
INTERNAL RAM
LOWER
128 BYTES
INTERNAL RAM
SPECIAL
FUNCTION
REGISTER
100
FF
00
FF
00
80
EXTERNAL
DATA
MEMORY
FFFF
0000
SU01293
Figure 33. Internal and External Data Memory Address Space with EXTRAM = 0
HARDWARE WATCHDOG TIMER (ONE-TIME
ENABLED WITH RESET-OUT FOR
P87C51RA2/RB2/RC2/RD2)
The WDT is intended as a recovery method in situations where the
CPU may be subjected to software upset. The WDT consists of a
14-bit counter and the WatchDog Timer reset (WDTRST) SFR. The
WDT is disabled at reset. To enable the WDT, the user must write
01EH and 0E1H in sequence to the WDTRST, SFR location 0A6H.
When the WDT is enabled, it will increment every machine cycle
while the oscillator is running and there is no way to disable the
WDT except through reset (either hardware reset or WDT overflow
reset). When the WDT overflows, it will drive an output reset HIGH
pulse at the RST-pin (see the note below).
Using the WDT
To enable the WDT, the user must write 01EH and 0E1H in sequence
to the WDTRST, SFR location 0A6H. When the WDT is enabled, the
user needs to service it by writing 01EH and 0E1H to WDTRST to
avoid a WDT overflow. The 14-bit counter overflows when it reaches
16383 (3FFFH) and this will reset the device. When the WDT is
enabled, it will increment every machine cycle while the oscillator is
running. This means the user must reset the WDT at least every
16383 machine cycles. To reset the WDT, the user must write 01EH
and 0E1H to WDTRST. WDTRST is a write only register. The WDT
counter cannot be read or written. When the WDT overflows, it will
generate an output RESET pulse at the reset pin (see note below).
The RESET pulse duration is 98
× TOSC (6-clock mode; 196 in
12-clock mode), where TOSC = 1/fOSC. To make the best use of the
WDT, it should be serviced in those sections of code that will
periodically be executed within the time required to prevent a WDT
reset.
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相關代理商/技術參數(shù)
參數(shù)描述
P87C51RD+4A 制造商:NXP Semiconductors 功能描述:IC 8BIT MCU OTP 64K 87C51 PLCC44
P87C51RD+4A,512 功能描述:8位微控制器 -MCU PREF PT P87C51RD2BA RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT
P87C51RD+4A 制造商:NXP Semiconductors 功能描述:IC 8BIT MCU OTP 64K 87C51 PLCC44
P87C51RD+4A512 制造商:NXP Semiconductors 功能描述:IC 8BIT MCU 80C51 16MHZ LCC-44
P87C51RD+4B 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:80C51 8-bit microcontroller family 8K-4K/256-1K OTP/ROM/ROMless, low voltage (2.7V-5.5V), low power, high speed (33 MHz)
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