80C51 8-bit microcontroller family 8KB/16KB/32KB/64K" />
參數(shù)資料
型號(hào): P87C51RA2BA,512
廠(chǎng)商: NXP Semiconductors
文件頁(yè)數(shù): 29/67頁(yè)
文件大小: 0K
描述: IC 80C51 MCU 512 RAM 44PLCC
產(chǎn)品培訓(xùn)模塊: Migrating from 8/16-Bit MCUs to 32-Bit ARMs
標(biāo)準(zhǔn)包裝: 26
系列: 87C
核心處理器: 8051
芯體尺寸: 8-位
速度: 33MHz
連通性: EBI/EMI,UART/USART
外圍設(shè)備: POR,PWM,WDT
輸入/輸出數(shù): 32
程序存儲(chǔ)器容量: 16KB(16K x 8)
程序存儲(chǔ)器類(lèi)型: OTP
RAM 容量: 512 x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 5.5 V
振蕩器型: 內(nèi)部
工作溫度: 0°C ~ 70°C
封裝/外殼: 44-LCC(J 形引線(xiàn))
包裝: 管件
其它名稱(chēng): 568-7904-5
568-7904-5-ND
568-8355-5
935271889512
P87C51RA2BA
P87C51RA2BA,512-ND
P87C51RA2BA-ND
Philips Semiconductors
Product data
P87C51RA2/RB2/RC2/RD2
80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP
with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high
speed (30/33 MHz)
2003 Jan 24
35
CMOD Address = D9H
Reset Value = 00XX X000B
CIDL
WDTE
CPS1
CPS0
ECF
Bit:
Symbol
Function
CIDL
Counter Idle control: CIDL = 0 programs the PCA Counter to continue functioning during idle Mode. CIDL = 1 programs
it to be gated off during idle.
WDTE
Watchdog Timer Enable: WDTE = 0 disables Watchdog Timer function on PCA Module 4. WDTE = 1 enables it.
Not implemented, reserved for future use.*
CPS1
PCA Count Pulse Select bit 1.
CPS0
PCA Count Pulse Select bit 0.
CPS1
CPS0
Selected PCA Input**
0
Internal clock, fOSC/6 in 6-clock mode (fOSC/12 in 12-clock mode)
0
1
Internal clock, fOSC/2 in 6-clock mode (fOSC/4 in 12-clock mode)
1
0
2
Timer 0 overflow
1
3
External clock at ECI/P1.2 pin
(max. rate = fOSC/4 in 6-clock mode, fOCS/8 in 12-clock mode)
ECF
PCA Enable Counter Overflow interrupt: ECF = 1 enables CF bit in CCON to generate an interrupt. ECF = 0 disables
that function of CF.
NOTE:
*
User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features. In that case, the reset or inactive
value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate.
** fOSC = oscillator frequency
SU01318
7
6
5
432
1
0
Figure 22. CMOD: PCA Counter Mode Register
CCON Address = D8H
Reset Value = 00X0 0000B
CF
CR
CCF4
CCF3
CCF2
CCF1
CCF0
Bit Addressable
Bit:
Symbol
Function
CF
PCA Counter Overflow flag. Set by hardware when the counter rolls over. CF flags an interrupt if bit ECF in CMOD is
set. CF may be set by either hardware or software but can only be cleared by software.
CR
PCA Counter Run control bit. Set by software to turn the PCA counter on. Must be cleared by software to turn the PCA
counter off.
Not implemented, reserved for future use*.
CCF4
PCA Module 4 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software.
CCF3
PCA Module 3 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software.
CCF2
PCA Module 2 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software.
CCF1
PCA Module 1 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software.
CCF0
PCA Module 0 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software.
NOTE:
*
User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features. In that case, the reset or inactive
value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate.
SU01319
76
5
4
3
210
Figure 23. CCON: PCA Counter Control Register
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