參數(shù)資料
型號(hào)： P87C51
廠商： NXP Semiconductors N.V.
英文描述： 80C51 8-bit microcontroller family 4K/128 OTP/ROM/ROMless low voltage (2.7V-5.5V),low power, high speed (33 MHz)(80C51 8位微控制器系列（4K/128 OTP/ROM/ROMless低電壓2.7V-5.5V，低功耗，高速33 MHz)
中文描述： 80C51的8位單片機(jī)系列4K/128檢察官辦公室/光盤/無(wú)ROM低電壓（2.7至5.5V），低功耗，高速（33兆赫）（80C51的8位微控制器系列（4K/128檢察官辦公室/光盤/無(wú)ROM低電壓為2.7V至5.5V，低功耗，高速33兆赫）
文件頁(yè)數(shù)： 19/38頁(yè)
文件大?。?/td> 350K
代理商： P87C51
Philips Semiconductors
Product specification
80C51/87C51/80C31
80C51 8-bit microcontroller family
4K/128 OTP/ROM/ROMless, low voltage (2.7V–5.5V),
low power, high speed (33 MHz)
2000 Jan 20
19
Reduced EMI Mode
The AO bit (AUXR.0) in the AUXR register when set disables the
ALE output.
Reduced EMI Mode
AUXR (8EH)
7
6
5
4
3
2
1
0
–
–
–
–
–
–
–
AO
AUXR.0
AO
Turns off ALE output.
Dual DPTR
The dual DPTR structure (see Figure 13) enables a way to specify
the address of an external data memory location. There are two
16-bit DPTR registers that address the external memory, and a
single bit called DPS = AUXR1/bit0 that allows the program code to
switch between them.
New Register Name: AUXR1#
SFR Address: A2H
Reset Value: xxx000x0B
AUXR1 (A2H)
7
6
5
4
3
2
1
0
–
–
–
LPEP
WUPD
0
–
DPS
Where:
DPS = AUXR1/bit0 = Switches between DPTR0 and DPTR1.
Select Reg
DPS
DPTR0
DPTR1
0
1
The DPS bit status should be saved by software when switching
between DPTR0 and DPTR1.
Note that bit 2 is not writable and is always read as a zero. This
allows the DPS bit to be quickly toggled simply by executing an INC
DPTR insstruction without affecting the WOPD or LPEP bits.
DPS
DPTR1
DPTR0
DPH
(83H)
DPL
(82H)
EXTERNAL
DATA
MEMORY
SU00745A
BIT0
AUXR1
Figure 13.
DPTR Instructions
The instructions that refer to DPTR refer to the data pointer that is
currently selected using the AUXR1/bit 0 register. The six
instructions that use the DPTR are as follows:
INC DPTR
Increments the data pointer by 1
MOV DPTR, #data16
Loads the DPTR with a 16-bit constant
MOV A, @ A+DPTR
Move code byte relative to DPTR to ACC
MOVX A, @ DPTR
Move external RAM (16-bit address) to
ACC
MOVX @ DPTR , A
Move ACC to external RAM (16-bit
address)
JMP @ A + DPTR
Jump indirect relative to DPTR
The data pointer can be accessed on a byte-by-byte basis by
specifying the low or high byte in an instruction which accesses the
SFRs. See application note AN458 for more details.
相關(guān)PDF資料
PDF描述
P80C51FA 80C51 8-bit microcontroller family 8K-64K/256-1K OTP/ROM/ROMless. low voltage 2.7V-5.5V). low power. high speed (33 MHz)
P80C54SFA 80C51 8-bit microcontroller family 8K-64K/256-1K OTP/ROM/ROMless. low voltage 2.7V-5.5V). low power. high speed (33 MHz)
P80C51FA-4B 80C51 8-bit microcontroller family 8K.64K/256.1K OTP/ROM/ROMless, low voltage 2.7V.5.5V, low power, high speed 33 MHz
P80C51FA-5A 80C51 8-bit microcontroller family 8K.64K/256.1K OTP/ROM/ROMless, low voltage 2.7V.5.5V, low power, high speed 33 MHz
P80C51SBBB 80C51 8-bit microcontroller family 4K/128 OTP/ROM/ROMless low voltage 2.7V.5.5V, low power, high speed 33 MHz
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