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參數(shù)資料
| 型號： | P87C380 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Microcontrollers for monitors with DDC interface, auto-sync detection and sync proc(帶DDC接口，同步監(jiān)測和同步處理的監(jiān)視器微控制器) |
| 中文描述： | 8-BIT, OTPROM, 16 MHz, MICROCONTROLLER, PDIP42 |
| 封裝： | 0.600 INCH, PLASTIC, SOT-270-1, SDIP-42 |
| 文件頁數(shù)： | 31/84頁 |
| 文件大小： | 420K |
| 代理商： | P87C380 |
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1997 Dec 12
31
Philips Semiconductors
Product specification
Microcontrollers for monitors with DDC
interface, auto-sync detection and sync proc.
P83Cx80; P87C380
Fig.14 PWM0 to PWM9 output patterns.
handbook, full pagewidth
4
MGG043
256
1
2
3
m
m
+
1
m
+
2
256
1
00
01
m
255
decimal value PWM data latch
14.2
14-bit PWM output (PWM10)
PWM10 shares the same pin as port line P1.7. Selection
of the pin function as either a PWM output or as a port line
is achieved using the PWME2.0 bit in SFR PWME2
(address E8H); see Table 4.
The block diagram for the 14-bit PWM output is shown in
Fig.15 and comprises:
Two 7-bit latches; SFRs PWM10H and PWM10L
14-bit data latch (PWMREG)
14-bit counter
Coarse pulse controller
Fine pulse controller
Mixer.
Data is loaded into the 14-bit data latch (PWMREG) from
the two 7-bit data latches (PWM10H and PWM10L) when
PWM10H is written to. The upper seven bits of PWMREG
are used by the coarse pulse controller and determine the
coarse pulse width; the lower seven bits are used by the
fine pulse controller and determine in which subperiods
fine pulses will be added.
The outputs OUT1 and OUT2 of the coarse and fine pulse
controllers are then ‘ORed’ in the mixer to give the PWM10
output. The polarity of the PWM10 output is programmable
and is selected by the P14LVL bit in SFR DFCON (address
C0H); see Section 7.3.2.
As the 14-bit counter is clocked by
1
4
f
clk
, the repetition
times of the coarse and fine pulse controllers may be
calculated as shown below.
Coarse controller repetition time:
Fine controller repetition time:
Figure 16 shows typical PWM10 outputs, with coarse
adjustment only, for different values held in PWM10H,
when P14LVL = 1. Figure 17 shows typical PWM10
outputs when P14LVL = 1, with coarse and fine
adjustment, after the coarse and fine pulse controller
outputs have been ‘ORed’ by the mixer.
When P14LVL = 1, the PWM10 output is inverted.
t
sub
128
f
clk
--4
×
=
t
r
128
128
clk
f
×
×
=
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